Abstract: Methods of forming cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include cross-coupling contacts. A sidewall spacer is formed adjacent to a gate structure, a dielectric cap is formed over the gate structure and the sidewall spacer, and an epitaxial semiconductor layer is formed adjacent to the sidewall spacer. A first portion of the dielectric cap is removed from over the sidewall spacer and the gate structure to expose a portion of a top surface of a gate electrode of the gate structure. A portion of the sidewall spacer is modified with an amorphization process. The modified portion of the sidewall spacer and the underlying gate dielectric layer are removed to expose a portion of a sidewall of the gate electrode. A cross-coupling contact is formed that directly connects the portions of the sidewall and top surface of the gate electrode with the epitaxial semiconductor layer.

Abstract: An optical display includes a display region and a non-display region. The optical display includes: an optical display element comprising a first substrate and a second substrate facing the first substrate, the second substrate having a metal interconnection layer thereon; and a first polarizing plate on an upper surface of the optical display element, wherein each of the first polarizing plate and the second substrate extends beyond the first substrate, the first polarizing plate includes a light shielding layer therein to conceal at least a portion of the metal interconnection layer, and the optical display further includes a securing member at a region surrounded by the first polarizing plate, the first substrate, and the second substrate.

Abstract: A plasma treatment is utilized prior to a conventional lift-off process to increase the hydrophilic characteristics of the surface of the sacrificial metal over the photoresist and minimize its ability to redeposit on the wafer surface. Highly-energized atoms (or molecules) in the plasma interact with the surface atoms of the metal, creating a temporary hydrophilic condition at the surface. This increased wettability of the metal layer surface thus minimizes the probability that subsequently removed thin film metal will be able to bond with the wafer surface. The metal layer may comprise a typical stack of Ti/Pt/Au, and the plasma treatment may use an O2-based plasma or a CF4-based plasma, among others.

Abstract: A light emitting device including a micro cavity having a phase modulation surface and a display apparatus including the light emitting device are provided. The light emitting device includes a reflective layer including a phase modulation surface; a first electrode disposed on the phase modulation surface of the reflective layer; a light emitting structure disposed on the first electrode; and a second electrode disposed on the light emitting structure. The phase modulation surface may include a plurality of nano scale patterns that are regularly or irregularly arranged. The reflective layer and the second electrode may constitute the micro cavity having a resonance wavelength of the light emitting device.

Abstract: An example embodiment may include a sensor for monitoring and/or measuring stress in a semiconductor component. The component may include a substrate formed of a semiconductor material. The substrate may include a planar main surface. The sensor may include at least one slanted surface of the substrate material, the slanted surface being defined by an oblique inclination angle with respect to the main surface of the substrate. The sensor may also include at least one straight resistive path extending on at least part of the slanted surface and a plurality of contacts and terminals for accessing the at least one resistive path. The contacts and terminals may allow for the measurement of an electrical resistance of the resistive path and an assessment of a shear stress in a plane that is not parallel to the main surface of the substrate.

Abstract: A semiconductor device includes gate structures formed transversely over semiconductor fins on a substrate. The gate material includes a gate conductor and a dielectric cap on the gate conductor. The device further includes unipolar spacers formed over the gate structures only. The semiconductor fins are free from the unipolar spacers, and the unipolar spacers have a substantially uniform thickness vertically along the gate structures and include a spacer material with an etch selectivity greater than SiN for oxide removal.

Abstract: An optical low-pass filter includes a stack of N (N?3) optical anisotropic layers each configured to separate an incident ray into a plurality of rays, wherein the following condition is satisfied: Ds?0.50 Da, where Da [?m] is a total value of ray separation widths of the first to (N?1)th optical anisotropic layers among the N optical anisotropic layers, and Ds [?m] is a distance between a ray having a maximum phase difference and a ray having a minimum phase difference among the rays separated by the first to (N?1)th optical anisotropic layers.

Abstract: Techniques for controlling top spacer thickness in VFETs are provided. In one aspect, a method of forming a VFET device includes: depositing a dielectric hardmask layer and a fin hardmask(s) on a wafer; patterning the dielectric hardmask layer and the wafer to form a fin(s) and a dielectric cap on the fin(s); forming a bottom source/drain at a base of the fin(s); forming bottom spacers on the bottom source/drain; forming a gate stack alongside the fin(s); burying the fin(s) in a dielectric fill material; selectively removing the fin hardmask(s); recessing the gate stack to form a cavity in the dielectric fill material; depositing a spacer material into the cavity; recessing the spacer material to form top spacers; removing the dielectric cap; and forming a top source/drain at a top of the fin(s). A VFET device is also provided.

Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.

Abstract: The present disclosure provides an organic light-emitting diode and a method for manufacturing the same, a display substrate and a method for manufacturing the same, and a display device. The organic light-emitting diode comprises a first electrode, a second electrode, and an organic light-emitting layer arranged between the first electrode and the second electrode, in which the second electrode is arranged close to the light-emitting side of the organic light-emitting diode, the first electrode includes a reflective conductive layer, and a surface of the reflective conductive layer close to the second electrode has an uneven structure.

Abstract: In a deep ultraviolet light-emitting device comprising a Group III nitride semiconductor, the concentrations of electrons and holes injected into a light-emitting layer is improved. A barrier layer has a last barrier layer closest to an electron blocking layer. The electron blocking layer has a first electron blocking layer closest to a light-emitting layer. The last barrier layer has a first position farthest from the first electron blocking layer, and a second position as an interface with the first electron blocking layer. The first electron blocking layer has a third position farthest from the last barrier layer. The Al composition ratio at the first position is higher than the Al composition ratio at the second position. The Al composition ratio at the third position is higher than the Al composition ratio at the first and second positions.

Abstract: A package structure includes a metal carrier, a conductive adhesive layer disposed on the metal carrier, a conductive post disposed on the conductive adhesive layer, a semiconductor chip disposed on the conductive adhesive layer and laterally spaced from the conductive post, and a redistribution layer disposed on the conductive post and the semiconductor chip. The semiconductor chip includes a first terminal at an upper surface of the semiconductor chip. The first terminal of the semiconductor chip is electrically connected to the bottom surface of the semiconductor chip through the redistribution layer, the conductive post and the conductive adhesive layer.

Abstract: An apparatus and associated method for high speed and/or mass transfer of electronic components onto a substrate comprises transferring, using an ejector assembly, electronics components (e.g., light emitting devices) from a die sheet onto an adhesive receiving structure to form a predefined pattern including electronic components thereon, and then transferring the electronic components defining the predefined pattern onto a substrate (e.g., a translucent superstrate) for light emission therethrough to create a high-density (e.g., high resolution) display device utilizing, for example, mini- or micro-LED display technologies.

Abstract: Exemplary embodiments are disclosed of thermal interface materials with wear-resisting layers and/or suitable for use between sliding components. Also disclosed are devices including thermal interface materials and methods of using thermal interface materials.

Abstract: Semiconductor devices and methods are provided to fabricate field effect transistor (FET) devices having local wiring between the stacked devices. For example, a semiconductor device includes a first FET device on a semiconductor substrate, the FET device comprising a first source/drain layer, and a first gate structure comprising a gate dielectric layer and a metal gate layer. The semiconductor device further includes a second FET device comprising a second source/drain layer, and a second gate structure comprising a gate dielectric layer and a metal gate layer; wherein the first and second FET devices are in a stacked configuration. The semiconductor device further includes one or more conductive vias in communication with either the first gate structure of the first FET device or the second gate structure of the second FET device.

Abstract: In accordance with an embodiment, microelectromechanical microphone includes a holder and a sound detection unit carried on the holder. The sound detection unit includes a planar first membrane, a planar second membrane arranged at a distance from the first membrane, a low-pressure chamber formed between the first membrane and the second membrane, a reduced gas pressure relative to normal pressure being present in the low-pressure chamber, a reference electrode arranged at least in sections in the low-pressure chamber, where the first and second membranes are displaceable relative to the reference electrode by sound waves to be detected, the reference electrode includes a planar base section and a stiffening structure provided on the base section, and the stiffening structure is provided on a side of the base section that faces the first membrane or/and on a side of the base section that faces the second membrane.

Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with silicon nitride. The silicon nitride situated above the first region is doped by ion implantation. Trenches are etched through the silicon nitride and the doped silicon nitride is partially etching in an isotropic manner. The trenches are filled with an insulator to a level situated above that of the first region. The silicon nitride is removed resulting in the edges of the first region only being covered with an insulator annulus.

Abstract: The semiconductor layer has a first surface, a second surface provided on opposite side from the first surface, and a third surface provided on the opposite side from the first surface with a step difference with respect to the second surface. The semiconductor layer includes a light emitting layer between the first surface and the third surface. The first electrode is in contact with the second surface. The second electrode is provided in a plane of the third surface. The second electrode includes a contact part in contact with the third surface and an end part not in contact with the third surface. The second electrode contains silver. The insulating film is provided between the end part of the second electrode and the third surface. A semiconductor light emitting device having a high light extraction efficiency is provided.

Abstract: A semiconductor module includes: a semiconductor device having an upper surface electrode; a conductor plate joined to the upper surface electrode via a bonding member; and a wire bonded to the conductor plate, wherein the wire is a metal thread or a ribbon bond, and the bonding member is a porous sintered metal material impregnated with resin.

Abstract: Embodiments of the invention include a microelectronic device that includes a transceiver coupled to a first substrate and a second substrate coupled to the first substrate. The second substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. An interposer substrate can provide a spacing between the first and second substrates.