Abstract: A silicon oxide liner, a silicon nitride liner, and a planarization silicon oxide layer may be sequentially formed over p-type and n-type field effect transistors. A patterned dielectric material layer covers an entirety of the n-type field effect transistor and does not cover at least a fraction of each area of p-doped active regions. An anisotropic etch process is performed to form p-type active region via cavities extending to a respective top surface of the p-doped active regions and n-type active region via cavities having a respective bottom surface at, or within, one of the silicon nitride liner and the silicon oxide liner. Boron-doped epitaxial pillar structures may be formed on top surfaces of the p-type active regions employing a selective epitaxy process. The n-type active region via cavities are extended to top surfaces of the n-doped active regions. Contact via structures are formed in the via cavities.

Abstract: Systems, methods and apparatus for coexistence of high voltage and low voltage devices and circuits on a same integrated circuit fabricated in silicon-on-insulator (SOI) technology are described. In particular, techniques for mitigating back gate effects are described, including using of resistive and/or capacitive couplings to control surface potentials at regions of a substrate used for the SOI fabrication proximate the high voltage and low voltage devices and circuits. In one case, an N-type implant is used to provide a high potential differential with respect to a substrate potential.

Abstract: A method of manufacturing semiconductor devices, including the steps of providing a substrate with a first active region, a second active region and a third active region, forming dummy gates in the first active region, the second active region and the third active region, removing the dummy gates to form trenches in the first active region, the second active region and the third active region, forming a high-k dielectric layer, a first bottom barrier metal layer on the high-k dielectric layer, a second bottom barrier metal layer on the first bottom barrier metal layer, and a first work function metal layer on the second bottom barrier metal layer in the trenches, removing the first work function metal layer from the second active region and the third active region, removing the second bottom barrier metal layer from the third region, and filling up each trench with a low resistance metal.

Abstract: A substrate and a manufacturing method thereof and a display device are provided. The substrate includes: a base including a bendable region; an interlayer on the base and in the bendable region; and a signal line at a side, facing away from the base, of the interlayer. In the bendable region, an orthographic projection of the signal line on the base is within an orthographic projection of the interlayer on the base; and in the bendable region, the interlayer is provided with a groove on at least one side of a portion, corresponding to the signal line, of the interlayer.

Abstract: A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack.

Abstract: A pixel structure includes a plurality of pixel units including three-primary-color sub-pixel groups and a plurality of fourth sub-pixels which are alternatively arranged. The fourth sub-pixel has a color different from that of the three-primary-color sub-pixel groups. The fourth sub-pixel is arranged between two adjacent three-primary-color sub-pixel groups.

Abstract: A substrate for a display device and a display device including the same are disclosed. The substrate includes a first thin-film transistor including an oxide semiconductor layer, a second thin-film transistor spaced apart from the first thin-film transistor and including a polycrystalline semiconductor layer, and a storage capacitor including at least two storage electrodes. One of the at least two storage electrodes is located in the same plane and is formed of the same material as gate electrodes of the first thin-film transistor and the second thin-film transistor, and another one of the at least two storage electrodes is located in the same plane and is formed of the same material as source and drain electrodes of the first thin-film transistor and the second thin-film transistor. Accordingly, lower power consumption and a larger area of the substrate are realized.

Abstract: A BCE TFT substrate includes a base substrate. A gate and a gate insulation layer are sequentially formed on the base substrate. An IGZO semiconductor layer is formed on the gate insulation layer to serve as an active layer. A source and a drain are disposed on the active layer and spaced from each other. Each of the source and drain is formed of a Mo layer, a Cu layer, and a conductorized IGZO film that are sequentially stacked on the active layer. A passivation layer is disposed on the source, the drain, and the active layer.

Abstract: An improved laterally diffused MOSFET (LDMOS) device enables an ability to tune some device parameters independently of other device parameters and/or provides a device architecture with component dimensions that significantly improve device performance. The LDMOS device includes a stepped gate having a first portion with a thin gate insulator over a body region and a second portion with a thick gate insulator over part of a drift region. In some embodiments, a gate shield is disposed over another part of the drift region to reduce a gate-drain capacitance of the LDMOS device. In some embodiments, the LDMOS device has a specific resistance (Rsp) of about 5-8 mOhm*mm2, a gate charge (Qg) of about 1.9-2.0 nC/mm2, and an Rsp*Qg product figure of merit of about 10-15 mOhm*nC.

Abstract: An exemplary embodiment of the present inventive concept provides a display device including: a thin film transistor panel comprising a display area and a peripheral area; and a color conversion panel overlapping the thin film transistor panel, wherein the color conversion panel includes: a substrate; a color conversion layer; a first organic layer disposed between the color conversion layer and the thin film transistor panel; a second organic layer disposed between the first organic layer and the thin film transistor panel; and a polarization layer disposed between the second organic layer and the thin film transistor panel, wherein the first organic layer overlaps the display area and the peripheral area, and the second organic layer overlaps the display area.

Abstract: An electronic device comprises a semiconductor chip, an accommodating part that accommodates the semiconductor chip, a plurality of terminals that are provided along a first side of a first surface and along a second side opposite to the first side with respect to the semiconductor chip, the plurality of terminals being electrically connected to the semiconductor chip and being exposed on the rectangular first surface of the accommodating part, and a plurality of conductive members that penetrate from the first surface of the accommodating part to the second surface opposite to the first surface.

Abstract: An OLED device and a method of preparing the same are provided, the OLED device including: a substrate; a first source electrode on the substrate, the first source electrode having a first side surface; a first insulating layer on the first source electrode, the first insulating layer having a second side surface intersecting with an upper surface of the first source electrode and the first side surface of the first source electrode, with at least one of an angle between the first side surface and the upper surface of the substrate and an angle between the second side surface and the upper surface of the substrate being an acute angle; an active layer on the substrate, the active layer covering the first side surface and the second side surface; a gate insulating layer on the active layer; an anode on the gate insulating layer; a light emitting functional layer on the anode; and a cathode on the light emitting functional layer, the cathode including a first drain region covering the first insulating layer and

Abstract: A method for manufacturing a tunnel junction layer using organic vapor phase deposition, the method including: a first process that supplies a first material gas containing a group III element, a second material gas containing a group V element, and a third material gas containing a dopant of a first conductivity type, onto a compound semiconductor layer on which the tunnel junction layer is to be laminated; a second process that stops supplying the first material gas, the second material gas and the third material gas, and supplies a fourth material gas containing a dopant of a second conductivity type opposite to the first conductivity type; and a third process that continues to supply the fourth material gas, and further supplies a fifth material gas containing a group III element and a sixth material gas containing a group V element.

Abstract: The present disclosure provides an organic light emitting diode (OLED) device and a method for manufacturing the same, an OLED display substrate and an OLED display device. The OLED device of the present disclosure comprises a substrate, and a first electrode, a light emitting layer and a second electrode arranged on the substrate, wherein the light emitting layer comprises fibers of p-phenylene based polymer as a host material, and the fibers of p-phenylene based polymer are arranged in a first orientation; and wherein the light emitted by the fibers of p-phenylene based polymer arranged in the first orientation is linearly polarized light in a first direction. The OLED device of the present disclosure can simultaneously ensure a good contrast, brightness and light transmittance.

Abstract: Body contact layouts for semiconductor structures are disclosed. In at least one exemplary embodiment, a semiconductor structure comprises: a plurality of gates disposed on a semiconductor layer, each gate extending parallel to a y-axis in a coordinate space; a source region disposed between two of the plurality of gates; a plurality of body contacts disposed in each source region; and wherein a portion of each source region, adjacent to the gate, has a width extending parallel to the y-axis that is greater than the width of the source region parallel to the y-axis at a distance on an x-axis from the gate.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to virtual drains for decreased harmonic generation in fully depleted SOI (FDSOI) RF switches and methods of manufacture. The structure includes one or more active devices on a semiconductor on insulator material which is on top of a substrate; and a virtual drain region composed of a well region within the substrate and spaced apart from an active region of the one or more devices, the virtual drain region configured to be biased to collect electrons which would accumulate in the substrate.

Abstract: An array substrate and a display device are provided.

Abstract: A display unit includes a first substrate, a transistor, first and second wiring layers, and an insulating film. The first substrate is provided with a display region and a peripheral region. The transistor is provided in the display region, and includes a semiconductor layer, a gate electrode facing the semiconductor layer, a gate insulating film between the gate electrode and the semiconductor layer, and a source-drain electrode electrically coupled to the semiconductor layer. The first wiring layer is provided in the peripheral region, electrically coupled to the transistor, and disposed closer to the first substrate than the same layer as the gate electrode and the source-drain electrode. The second wiring layer is provided on the first substrate and has an electric potential different from the first wiring layer. The insulating film is provided between the second wiring layer and the first wiring layer.

Abstract: A method of fabricating a semiconductor structure includes forming a plurality of Fin structures, doping first dopants at both sides of a first Fin structure of the Fin structures, and providing a first thermal diffusion operation to the semiconductor structure. The method also includes doping second dopants at both sides of a second Fin structure of the Fin structures, and providing a second thermal diffusion operation to the semiconductor structure. A first gate length for the first Fin structure is formed using the first and the second thermal diffusion operations, and a second gate length for the second Fin structure using the second thermal diffusion operation. The first dopants are of the same type or a different type.

Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.