Abstract: An organic light-emitting display device includes: a substrate; a pixel electrode on the substrate; an auxiliary electrode spaced apart from the pixel electrode; a first insulating film between the pixel electrode and the auxiliary electrode and covering an end of the pixel electrode and an end of the auxiliary electrode; an intermediate layer on the pixel electrode and including an emission layer; an opposite electrode covering the intermediate layer and contacting the auxiliary electrode; and a passivation layer covering the opposite electrode.

Abstract: A structure includes a first periodic structure positioned on a chip, the first periodic structure comprising a material of a first layer disposed on the chip. The structure further includes a second periodic structure positioned within the region of the chip adjacent the first periodic structure, the second periodic structure comprising a second material of a second layer disposed on the chip. The structure further includes an acoustic wave transmitter device disposed on the chip and an acoustic wave receiver device disposed on the chip.

Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area, and a pn junction diode electrically connected in series with the resistor. A method of producing the semiconductor device is also described.

Abstract: Methods for forming a tight pitch stack nanowire without shallow trench isolation including a base nanosheet formed on a substrate. At least one fin are formed, and at least one dummy gate is formed over the at least two fins, on the base nanosheet, the at least two fins including at least two alternating layers of a first material and a second material. The base nanoset is replaced with a blanket dielectric to form a shallow trench isolation (STI) around the at least one fin and around the at least one dummy gate. A gate replacement is performed to replace the at least one dummy gate and the second material with a gate conductor material and a gate cap to form gate structure.

Abstract: An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.

Abstract: A semiconductor structure includes a conductive structure, a dielectric layer, and a plurality of conductive features. The dielectric layer is present on the conductive structure. The dielectric layer has a plurality of through holes therein, and at least one of the through holes exposes the conductive structure. The conductive features are respectively present in the through holes. At least one of the conductive features has a bottom surface and at least one sidewall. The bottom surface and the sidewall of the conductive feature intersect to form an interior angle. The interior angles of adjacent two of the conductive features have a difference less than or substantially equal to about 3 degrees.

Abstract: A vertical trench shield device can include a plurality of gate structures and a termination structure surrounding the plurality of gate structures. The plurality of gate structures can include a plurality of gate regions and a corresponding plurality of gate shield regions. The plurality of gate structures can be disposed between the plurality of source regions, and extending through the plurality of body regions to the drift region. The plurality of gate structures can be separated from each other by a first predetermined spacing in a core area. A first set of the plurality of gate structures can extend fully to the termination structure. The ends of a second set of the plurality of gate structures can be separated from the termination structure by a second predetermined spacing. The first and second spacings can be configured to balance charge in the core area and the termination area in a reverse bias condition.

Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.

Abstract: An example of a pixel module comprises a module substrate having light emitters disposed on a light-emitter surface and a controller disposed on a controller surface opposed to the light-emitter surface. At least one module electrode is electrically connected to the controller and at least one module electrode is electrically connected to each light emitter. An example of a pixel-module wafer comprises a module source wafer comprising sacrificial portions and module anchors, each sacrificial portion laterally separated from an adjacent sacrificial portion by a module anchor and a pixel module disposed entirely over each sacrificial portion. At least one module tether physically connects each of the pixel modules to at least one of the module anchors. An example of a pixel-module display comprises a display substrate, pixel modules disposed on the display substrate and display electrodes disposed on the display substrate, each display electrode electrically connected to a module electrode.

Abstract: An organic light emitting diode (OLED) display includes: a first electrode around a center point of a virtual tetragon, e.g., a virtual square; second electrodes around a first vertex and a second vertex diagonal to the first vertex of the virtual square, the second electrodes being separated from each other and with the center point of the virtual square interposed therebetween; third electrodes around a third vertex and a fourth vertex of the virtual square, the third electrodes being separated from each other and with the center point of the virtual square interposed therebetween; a pixel defining layer partially on the first electrode, the second electrodes, and the third electrodes, and partially exposing the first electrode, the second electrodes, and the third electrodes; and four spacers disposed as islands on the pixel defining layer and corresponding to four sides of the virtual square.

Abstract: In accordance with an embodiment, a microelectromechanical transducer includes a displaceable membrane having an undulated section comprising at least one undulation trough and at least one undulation peak and a plurality of piezoelectric unit cells. At least one piezoelectric unit cell is provided in each case in at least one undulation trough and at least one undulation peak, where each piezoelectric unit cell has a piezoelectric layer and at least one electrode in electrical contact with the piezoelectric layer. The membrane may be formed as a planar component having a substantially larger extent in a first and a second spatial direction, which are orthogonal to one another, than in a third spatial direction, which is orthogonal to the first and the second spatial direction and defines an axial direction of the membrane.

Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.

Abstract: Each of a plurality of the light-emitting units (140) includes a first electrode (110), an organic layer (120), and a second electrode (130). The first electrode (110) is light-transmitting, and the second electrode (130) is light-reflective. The organic layer (120) is located between the first electrode (110) and the second electrode (130). The light-transmitting regions (104 and 106) are located between the plurality of light-emitting units (140). A sealing member (170) covers the plurality of light-emitting units (140) and the light-transmitting regions (104 and 106). The sealing member (170) is fixed directly or through an insulating layer (174) to at least one of a structure (for example, the second electrode 130) formed on a substrate (100), and the substrate (100). In addition, a haze value of the light-emitting device (10) is equal to or less than 2.0%, preferably equal to or less than 1.4%.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a stacked wire structure formed over the substrate. The semiconductor device structure also includes a gate structure formed over a middle portion of the stacked wire structure and a source/drain (S/D) structure formed at two opposite sides of the stacked wire structure. The S/D structure includes a top surface, a sidewall surface, and a rounded corner between the top surface and the sidewall surface.

Abstract: According to one embodiment, a semiconductor device includes an oxide semiconductor layer, a first electrode, a second electrode, and a control electrode. The oxide semiconductor layer includes tin and tungsten. An average coordination number of oxygen atoms to tin atoms is greater than 3 but less than 4. The first electrode is electrically connected to a first end portion of the oxide semiconductor layer. The second electrode is electrically connected to a second end portion of the oxide semiconductor layer on a side opposite to the first end portion. The control electrode opposes a portion of the oxide semiconductor layer between the first end portion and the second end portion.

Abstract: An apparatus including a three-dimensional semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the three-dimensional semiconductor body including a plurality of nanowires including a germanium material disposed in respective planes separated in the junction regions by a second material, wherein a lattice constant of the second material is similar to a lattice constant of the germanium material; and a gate stack disposed on the channel region, the gate stack including a gate electrode disposed on a gate dielectric. A method of including forming a plurality of nanowires in separate planes on a substrate, each of the plurality of nanowires including a germanium material and separated from an adjacent nanowire by a sacrificial material; disposing a gate stack on the plurality of nanowires in a designated channel region, the gate stack including a dielectric material and a gate electrode.

Abstract: A display device includes a display panel including a plurality of light emitters spaced apart by a first representative distance in a first emission region and a plurality of light emitters spaced apart by a second representative distance different from the first representative distance in a second emission region that surrounds the first emission region. The display device also includes a filter coupled with the display panel for transmitting light projected by the display panel through the filter. The filter has a first filter region configured to cause a first distribution of light emitted from a first light emitter in the first emission region and a second distribution of light emitted from a second light emitter in the first emission region so that the first distribution at least partially overlaps with the second distribution.

Abstract: LEDs and methods of forming LEDs with various structural configurations to mitigate non-radiative recombination at the LED sidewalls are described. The various configurations described include combinations of LED sidewall surface diffusion with pillar structure, modulated doping profiles to form an n-p superlattice along the LED sidewalls, and selectively etched cladding layers to create entry points for shallow doping or regrowth layers.

Abstract: A semiconductor device includes a first transistor in a first region and a second transistor in a second region. The first transistor includes: a first nanowire, a first gate electrode, a first gate dielectric layer, a first source/drain region, and an inner-insulating spacer. The first nanowire has a first channel region. The first gate electrode surrounds the first nanowire. The first gate dielectric layer is between the first nanowire and the first gate electrode. The first source/drain region is connected to an edge of the first nanowire. The inner-insulating spacer is between the first gate dielectric layer and the first source/drain region. The second transistor includes a second nanowire, a second gate electrode, a second gate dielectric layer, and a second source/drain region. The second nanowire has a second channel region. The second gate electrode surrounds the second nanowire. The second gate dielectric layer is between the second nanowire and the second gate electrode.

Abstract: A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.