Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a variable resistance element that exhibits different resistance states for storing data; and a lower contact plug coupled to the variable resistance element and disposed under the variable resistance element, and wherein a width of the lower contact plug increases from a top surface of the lower contact plug to a bottom surface of the lower contact plug.

Abstract: An oxide semiconductor film which has more stable electric conductivity is provided. The oxide semiconductor film comprises a crystalline region. The oxide semiconductor film has a first peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.4 nm?1 and less than or equal to 0.7 nm?1 in a region where a magnitude of a scattering vector is greater than or equal to 3.3 nm?1 and less than or equal to 4.1 nm?1. The oxide semiconductor film has a second peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.45 nm?1 and less than or equal to 1.4 nm?1 in a region where a magnitude of a scattering vector is greater than or equal to 5.5 nm?1 and less than or equal to 7.1 nm?1.

Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.

Abstract: A white light source includes an arrangement of light-emitting diodes, wherein the light-emitting diodes are subdivided into first light-emitting diodes and second light-emitting diodes, and a conversion element configured to absorb light emitted by the light-emitting diodes and generate converted light with a longer wavelength than the emitted light, wherein the conversion element includes a first luminescent conversion material in a first matrix material, the first matrix material with the first luminescent conversion material is arranged two-dimensionally in a continuous layer above the first and second light-emitting diodes, the conversion element includes a second luminescent conversion material in a second matrix material, and the second matrix material with the second luminescent conversion material is arranged only above the second light-emitting diodes.

Abstract: A method for fabricating a semiconductor device including a vertically oriented memory structure includes forming at least one pillar including phase-change memory (PCM) material on at least one electrode, forming a plurality of spacers on the electrode and along sidewalls of the pillar, and forming, by processing the plurality of spacers and the pillar, a modified pillar having a vertically oriented dumbbell shape associated with a vertically oriented PCM memory structure.

Abstract: A thin film transistor array substrate includes a substrate, at least one thin film transistor, a capacitor, an interlayer insulating layer, and a node connection line. The at least one thin film transistor is on the substrate. The capacitor is on the substrate and includes: a bottom electrode on the substrate; a top electrode overlapping the bottom electrode, the top electrode including an opening having a single closed curve shape; and a dielectric layer between the bottom electrode and the top electrode. The interlayer insulating layer covers the capacitor. The node connection line is on the interlayer insulating layer and electrically connects the capacitor to the at least one thin film transistor. An overlapping area of the bottom electrode and the top electrode is divided by the opening into two separate areas.

Abstract: Presented is a lateral fin static induction transistor including a semi conductive substrate, source and drain regions extending from an optional buffer layer of same or varied thickness supported by the semi conductive substrate, a semi conductive channel electrically coupling the source region to the drain region of the transistor, a portion of the semi conductive channel being a fin and having a face covered by a gated structure, thereby defining a gated channel within the semi conductive channel, the semi conductive channel further including a drift region electrically coupling the gated channel to the drain region of the transistor.

Abstract: Disclosed is an embedded multi-die interconnect bridge (EMIB) substrate. The EMIB substrate can comprise an organic substrate, a bridge embedded in the organic substrate and a plurality of routing layers. The plurality of routing layers can be embedded within the bridge. Each routing layer can have a plurality of traces. Each of the plurality of routing layers can have a coefficient of thermal expansion (CTE) that varies from an adjacent routing layer.

Abstract: A silicon carbide body includes a drift structure having a first conductivity type, a body region, and a shielding region. The body and shielding regions, of a second conductivity type, are located between the drift structure and a first surface of the silicon carbide body. First and second trench gate stripes extend into the silicon carbide body. The body region is in contact with a first sidewall of the first trench gate stripe. The shielding region is in contact with a second sidewall of the second trench gate stripe. The second sidewall has a first length in a lateral first direction parallel to the first surface. A supplementary region of the first conductivity type contacts one or more interface areas of the second sidewall. The one or more interface areas have a combined second length along the first direction, the second length being at most 40% of the first length.

Abstract: A three-dimensional semiconductor device is disclosed. The device may include an electrode structure that can include a plurality of electrodes that are stacked on a substrate and extend in a first direction. Vertical structures can penetrate the electrode structure to provide a plurality of columns spaced apart from each other in a second direction crossing the first direction. The plurality of columns can include first and second edge columns located adjacent to respective opposite edges of the electrode structure, and the plurality of columns can include a center column located between the first and second edge columns. Distances between adjacent ones of the plurality of columns can decrease in a direction from the first and second edge columns toward the center column.

Abstract: Novel microlens array architectures for enhanced light outcoupling from light emission are provided. Organic light emitting devices (OLEDs) that include an outcoupling layer including these novel microlens array architectures and method for fabricating such OLEDs are provided. These devices may be used to provide OLEDs with optimized light extraction.

Abstract: A display panel and a manufacturing method thereof. The display panel includes a base substrate, and a pixel area and a non-pixel area on the substrate. The pixel area includes a light emitting element, the light emitting element including a first electrode, a light emitting layer, and a second electrode which are sequentially on the base substrate; the non-pixel area includes a first structural area, the first structural area including a conductive supporting block on one side of the light emitting layer close to the base substrate; the display panel further includes an electric connection layer which is on one side, which is away from the base substrate, of the light emitting element and the first structural area; the second electrode of the light emitting element is electrically connected with the electric connection layer, and is electrically connected with the conductive supporting block through the electric connection layer.

Abstract: [Object] To achieve a high-sensitivity radiation detector. [Solution] An amplifying transistor (3) is configured such that a photodiode (1) receives light with the amplifying transistor (3) conductive.

Abstract: A phosphor containing particle including a core portion which is a particulate matter of resin including a constitutional unit derived from an ionic liquid with a semiconductor nanoparticle phosphor dispersed therein and a shell portion which is a matter in a form of a layer of resin which includes a constitutional unit derived from an ionic liquid and coats at least a portion of the core portion, and a phosphor containing particle including a particulate matter of resin including a constitutional unit derived from an ionic liquid with a semiconductor nanoparticle phosphor dispersed therein and a metal oxide layer coating at least a portion of the particulate matter of resin. A light emitting device including a light source and a wavelength converter in which phosphor containing particles are dispersed in a translucent medium, and a phosphor containing sheet in which phosphor containing particles are dispersed in a sheet-shaped translucent medium.

Abstract: There is provided a solid-state imaging device capable of reducing the number of wiring layers and achieving downsizing with flexible layout designing. The solid-state imaging device includes a first semiconductor chip including a first electrode pad, first wiring connected to a first electrode pad through a first via, and a logic circuit, which are formed therein, and a second semiconductor chip connected to the first semiconductor chip and including a second electrode pad, second wiring connected to the second electrode pad through a second via, and a pixel array, which are formed therein. The first electrode pad and the second electrode pad are bonded as being shifted from each other on a bonding surface of the first semiconductor chip and the second semiconductor chip.

Abstract: An optical element includes: a base; and an uneven structure layer that is disposed on at least one face of the base, and suppresses reflectance, the optical element having a reflectance of 1% or smaller, in a wavelength region of 400 nm or longer and 700 nm or shorter, a transmittance of 90% or larger, in a wavelength region of 470 nm or longer and 550 nm or shorter, and a variation of transmittance of 1% or smaller, between before and after a high-temperature environmental test conducted at 150° C. for 250 h.

Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. A plurality of logic devices is disposed on the logic region. A sidewall spacer is disposed along a sidewall surface of the logic devices, but not disposed along a sidewall surface of the memory cell structures. Thus, the inter-layer dielectric (ILD) fill-in window between adjacent memory cell structures is enlarged, compared to the approaches where the sidewall spacer is concurrently formed in both memory region and the logic region. Thereby, voids formation would be reduced or eliminated, and device quality would be improved.

Abstract: An electroluminescent device including an electrode, the electrode being ionically conductive; an electroluminescence layer positioned adjacent or in contact with the electrode, the electroluminescence layer being electrically coupled to the electrode; the electroluminescence layer receiving electrical energy from the electrode and illuminating in response to received electrical energy, and wherein the electrode and the electroluminescence layer are repairable such that the function of the electrode and the electroluminescence layer is restored after a deformation.

Abstract: An IC structure includes a first plurality of metal segments in a first metal layer, a second plurality of metal segments in a second metal layer overlying the first metal layer, and a third plurality of metal segments in a third metal layer overlying the second metal layer. The metal segments of the first and third pluralities of metal segments extend in a first direction, and the metal segments of the second plurality of metal segments extend in a second direction perpendicular to the first direction. A pitch of the third plurality of metal segments is smaller than a pitch of the second plurality of metal segments.

Abstract: A display device is disclosed, which may prevent a dark spot defect caused by water permeation from occurring and reduce accumulated stress. The display device comprises a substrate having a barrier pattern; and a thin film transistor provided on the substrate.