Patents Examined by Dung Le
-
Patent number: 10361336Abstract: In one aspect, there is provided an apparatus including a light emitting diode. The apparatus may include a plurality of layers including a substrate layer, a buffer layer disposed on the substrate layer, a charge transport layer, a light emission layer, another charge transport layer, and/or a metamaterial layer. The other charge transport layer may have at least one channel etched into the other charge transport layer leaving a residual thickness of the other charge transport layer between a bottom of the etched channel and the light emission layer. A metamaterial layer may be contained in the at least one channel that is proximate to the residual thickness of the charge transport layer. The metamaterial may include a structure including at least one of a dielectric or a metal. The metamaterial may cause the light emitting diode to operate at higher frequencies and with higher efficiency.Type: GrantFiled: November 28, 2017Date of Patent: July 23, 2019Assignee: The Regents of the University of CaliforniaInventors: Zhaowei Liu, Danyong Dylan Lu
-
Patent number: 10229992Abstract: Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes a buffer layer composed of a first nitride semiconductor layer, a channel layer composed of a second nitride semiconductor layer, and a barrier layer composed of a third nitride semiconductor layer, which are sequentially laminated, and a cap layer composed of a fourth nitride semiconductor layer of mesa type, which is formed over the barrier layer. The semiconductor device also includes a source electrode formed on one side of the cap layer, a drain electrode formed on the other side of the cap layer, and a first gate electrode formed over the cap layer. The first gate electrode and the cap layer are Schottky-joined. A Schottky gate electrode (the first gate electrode) is provided over the cap layer in this way, so that when a gate voltage is applied, an electric field is applied to the entire cap layer and a depletion layer spreads. Therefore, it is possible to suppress a gate leakage current.Type: GrantFiled: February 26, 2018Date of Patent: March 12, 2019Assignee: Renesas Electronics CorporationInventors: Yoshinao Miura, Hironobu Miyamoto
-
Patent number: 10229997Abstract: Techniques are disclosed for forming high mobility NMOS fin-based transistors having an indium-rich channel region electrically isolated from the sub-fin by an aluminum-containing layer. The aluminum aluminum-containing layer may be provisioned within an indium-containing layer that includes the indium-rich channel region, or may be provisioned between the indium-containing layer and the sub-fin. The indium concentration of the indium-containing layer may be graded from an indium-poor concentration near the aluminum-containing barrier layer to an indium-rich concentration at the indium-rich channel layer. The indium-rich channel layer is at or otherwise proximate to the top of the fin, according to some example embodiments. The grading can be intentional and/or due to the effect of reorganization of atoms at the interface of indium-rich channel layer and the aluminum-containing barrier layer. Numerous variations and embodiments will be appreciated in light of this disclosure.Type: GrantFiled: June 23, 2015Date of Patent: March 12, 2019Assignee: INTEL CORPORATIONInventors: Chandra S. Mohapatra, Anand S. Murthy, Glenn A. Glass, Tahir Ghani, Willy Rachmady, Jack T. Kavalieros, Gilbert Dewey, Matthew V. Metz, Harold W. Kennel
-
Patent number: 10229866Abstract: Techniques are disclosed for providing on-chip capacitance using through-body-vias (TBVs). In accordance with some embodiments, a TBV may be formed within a semiconductor layer, and a dielectric layer may be formed between the TBV and the surrounding semiconductor layer. The TBV may serve as one electrode (e.g., anode) of a TBV capacitor, and the dielectric layer may serve as the dielectric body of that TBV capacitor. In some embodiments, the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor. To that end, in some embodiments, the entire semiconductor layer may comprise a low-resistivity material, whereas in some other embodiments, low-resistivity region(s) may be provided just along the sidewalls local to the TBV, for example, by selective doping in those location(s). In other embodiments, a conductive layer formed between the dielectric layer and the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor.Type: GrantFiled: June 22, 2015Date of Patent: March 12, 2019Assignee: Intel CorporationInventors: Yi Wei Chen, Kinyip Phoa, Nidhi Nidhi, Jui-Yen Lin, Kun-Huan Shih, Xiaodong Yang, Walid M. Hafez, Curtis Tsai
-
Patent number: 10224305Abstract: In order to inhibit defective connection between a bump of a semiconductor chip and an electrode pad of a substrate, a semiconductor device includes a substrate provided on a surface with a plurality of electrode pads 15, a semiconductor chip 20 provided on a surface with a plurality of bumps 21 substantially equal in size, and an anisotropic conductive film 30 interposed between the plurality of bumps 21 and the plurality of electrode pads 15 and electrically connecting each of the bumps 21 and corresponding one of the electrode pads 15. The plurality of electrode pads 15 includes a plurality of first electrode pads 15A positioned closest to an end 25 of the semiconductor chip 20, and a plurality of second electrode pads 15B positioned inside the plurality of first electrode pads 15A on the semiconductor chip 20. Each of the second electrode pads 15B is larger in area than each of the first electrode pads 15A.Type: GrantFiled: May 18, 2016Date of Patent: March 5, 2019Assignee: SHARP KABUSHIKI KAISHAInventors: Masaki Nakayama, Motoji Shiota, Takashi Matsui, Yasuhiko Tanaka, Hiroki Miyazaki, Seiji Muraoka
-
Patent number: 10217905Abstract: Disclosed according to one embodiment is a light-emitting element comprising: a light-emitting structure comprising a first semiconductor layer, an active layer, and a second semiconductor layer; a second conductive layer electrically connected to the second semiconductor layer; a first conductive layer comprising a plurality of through electrodes electrically connected to the first semiconductor layer through the second conductive layer and the light-emitting structure; an insulation layer for electrically insulating the plurality of through electrodes from the active layer, the second semiconductor layer, and the second conductive layer; and an electrode pad disposed in an exposed area of the second conductive layer, wherein the plurality of through electrodes differ in the area of a first region electrically connected to the first semiconductor layer.Type: GrantFiled: May 25, 2016Date of Patent: February 26, 2019Assignee: LG INNOTEK CO., LTD.Inventors: Sun Woo Park, Dong Hyun Sung, Dae Hee Lee, Byoung Woo Lee, Kwang Ki Choi, Jae Cheon Han
-
Patent number: 10217695Abstract: An electronic device comprising a semiconductor package having a first main surface region and a second main surface region and comprising a semiconductor chip comprising at least one chip pad in the second main surface region and a connector block comprising at least one first electrically conductive through connection and at least one second electrically conductive through connection extending with different cross-sectional areas between the first main surface region and the second main surface region and being arranged side-by-side with the semiconductor chip.Type: GrantFiled: December 2, 2016Date of Patent: February 26, 2019Assignee: Infineon Technologies AGInventors: Thorsten Meyer, Klaus Pressel, Maciej Wojnowski
-
Patent number: 10211109Abstract: Semiconductor devices and methods are provided to fabricate field effect transistor (FET) devices having local wiring between the stacked devices. For example, a semiconductor device includes a first FET device on a semiconductor substrate, the FET device comprising a first source/drain layer, and a first gate structure comprising a gate dielectric layer and a metal gate layer. The semiconductor device further includes a second FET device comprising a second source/drain layer, and a second gate structure comprising a gate dielectric layer and a metal gate layer; wherein the first and second FET devices are in a stacked configuration. The semiconductor device further includes one or more conductive vias in communication with either the first gate structure of the first FET device or the second gate structure of the second FET device.Type: GrantFiled: November 29, 2017Date of Patent: February 19, 2019Assignee: International Business Machines CorporationInventor: Effendi Leobandung
-
Patent number: 10211335Abstract: A power transistor is provided with at least one transistor finger that lies within a semiconductor material. The gate oxide is segmented into a set of segments with thick field oxide between each segment in order to reduce gate capacitance and thereby improve a resistance times gate charge figure of merit.Type: GrantFiled: December 4, 2017Date of Patent: February 19, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sameer Pendharkar, Ming-yeh Chuang
-
Patent number: 10199445Abstract: There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size and/or utilize the side surface of an assembled flexible display.Type: GrantFiled: March 5, 2018Date of Patent: February 5, 2019Assignee: LG Display Co., Ltd.Inventors: SeYeoul Kwon, HeeSeok Yang, Sangcheon Youn, SungWoo Kim, YoonDong Cho, Saemleenuri Lee
-
Patent number: 10199354Abstract: A stacked-chip assembly including an IC chip or die that is electrically interconnected to another chip and/or a substrate by one or more traces that are coupled through sidewalls of the chip. Electrical traces extending over a sidewall of the chip may contact metal traces of one or more die interconnect levels that intersect the chip edge. Following chip fabrication, singulation may expose a metal trace that intersects the chip sidewall. Following singulation, a conductive sidewall interconnect trace formed over the chip sidewall is to couple the exposed trace to a top or bottom side of a chip or substrate. The sidewall interconnect trace may be further coupled to a ground, signal, or power rail. The sidewall interconnect trace may terminate with a bond pad to which another chip, substrate, or wire lead is bonded. The sidewall interconnect trace may terminate at another sidewall location on the same chip or another chip.Type: GrantFiled: December 20, 2016Date of Patent: February 5, 2019Assignee: Intel CorporationInventors: Mitul Modi, Digvijay A. Raorane
-
Patent number: 10199466Abstract: A semiconductor device of an embodiment includes a silicon carbide layer including a first plane and a second plane; a trench including a first side face, a second side face, and a bottom face; a first silicon carbide region of a first-conductivity type; a second silicon carbide region of a second-conductivity type; a third silicon carbide region of the second-conductivity type sandwiching the trench with the second silicon carbide region; a sixth silicon carbide region of the second-conductivity type being in contact with the second side face and the bottom face; a gate electrode; and an insulating layer between the gate electrode and the second silicon carbide region, in which a portion of the first side face being in contact with the first silicon carbide region includes a first, second, and third region, and inclination angle of the second region is shallower than those of the first and third regions.Type: GrantFiled: February 27, 2018Date of Patent: February 5, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Shinya Kyogoku, Ryosuke Iijima
-
Patent number: 10191339Abstract: Provided is a BOA liquid crystal panel based on an IGZO-TFT and a method for manufacturing the same. The method includes steps of: (1) forming a black matrix; (2) forming a gate; (3) forming a gate insulator; (4) forming a source and a drain; (5) forming IGZO; (6) forming a passivation; (7) forming R/G/B color resist; (8) forming ITO. Copper oxide is used as a coplanar structure of the black matrix of an IGZO-TFT based BOA component, which can effectively prevent the risk of etching IGZO.Type: GrantFiled: January 5, 2017Date of Patent: January 29, 2019Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventor: Longqiang Shi
-
Patent number: 10193104Abstract: The present disclosure provides an organic light-emitting diode device (OLED) structure for compensating blue light emission. The OLED structure includes a substrate with a thin-film transistor layer, the substrate being substantially transparent; and a first electrode layer on the substrate, the first electrode being substantially transparent; a first light-emitting layer on the first electrode layer with one or more light-emitting portions for emitting light for compensating blue light. The OLED structure also includes a charge generation layer (CGL) with a reflective portion, the CGL on the first light-emitting layer, the reflective portion having a transmission rate for light emitted by the first light-emitting layer; a second light-emitting layer on the CGL with one or more light-emitting portions for emitting the blue light; and a second electrode layer with a reflectivity on the second light-emitting layer.Type: GrantFiled: October 29, 2015Date of Patent: January 29, 2019Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Kai Xu, Xinwei Gao
-
Patent number: 10192993Abstract: The present disclosure provides a TFT, a manufacturing method thereof, an array substrate and a manufacturing method thereof. The TFT includes a substrate, a p-Si active layer arranged on the substrate, and a first a-Si layer arranged on a surface of the p-Si active layer at a side adjacent to the substrate. An orthogonal projection of the p-Si active layer onto the substrate at least partially overlaps an orthogonal projection of the first a-Si layer onto the substrate.Type: GrantFiled: September 14, 2017Date of Patent: January 29, 2019Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.Inventors: Yanwei Ren, Chaochao Sun, Kunpeng Zhang, Yezhou Fang, Jingyi Xu
-
Patent number: 10186508Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.Type: GrantFiled: October 24, 2017Date of Patent: January 22, 2019Assignee: Infineon Technologies AGInventors: Dirk Ahlers, Markus Zundel, Peter Brandl, Kurt Matoy, Thomas Ostermann
-
Patent number: 10186633Abstract: A method of manufacturing a light emitting device includes: forming a light-transmissive member that is substantially rectangular in a plan view to cover an upper surface of a light emitting element mounted on a base member; and forming a frame body so as to surround the light-transmissive member, wherein, in the step of forming the frame body, the frame body is formed such that a distance from an upper surface of the base member to an upper end of the frame body is smaller along a short side of the light-transmissive member than along a long side of the light-transmissive member.Type: GrantFiled: August 22, 2017Date of Patent: January 22, 2019Assignee: NICHIA CORPORATIONInventors: Satoshi Shichijo, Kunihito Sugimoto, Kenji Ozeki, Shogo Abe
-
Patent number: 10170619Abstract: A semiconductor structure containing a vertical Schottky contact transistor is provided in which the contact resistance as well as the junction resistance is improved. The vertical Schottky contact transistor includes a bottom Schottky contact source/drain structure and a top Schottky contact source/drain structure located at opposing ends of a semiconductor channel region. The bottom Schottky contact source/drain structure includes a base portion and a vertically extending portion.Type: GrantFiled: August 22, 2017Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
-
Patent number: 10170586Abstract: A method for forming a spacer for a semiconductor device includes patterning gate material in a transverse orientation relative to semiconductor fins formed on a substrate and conformally depositing a dummy spacer layer over surfaces of gate structures and the fins. A dielectric fill formed over the gate structures and the fins is planarized to remove a portion of the dummy spacer layer formed on tops of the gate structures and expose the dummy spacer layer at tops of the sidewalls of the gate structures. Channels are formed by removing the dummy spacer layer along the sidewalls of the gate structures. The fins are protected by the dielectric fill. A spacer is formed by filling the channels with a spacer material. The dielectric fill and the dummy spacer layer are removed to expose the fins. Source and drain regions are formed between the gate structures on the fins.Type: GrantFiled: October 19, 2017Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Peng Xu, Jie Yang
-
Patent number: 10163731Abstract: A FinFET semiconductor structure includes first fins and second fins extended from a semiconductor substrate, and a gate structure disposed over the first fins and the second fins. Each first fin includes a first semiconductor portion connected to the semiconductor substrate and a second semiconductor portion over the semiconductor substrate. Each second fin includes the first semiconductor portion connected to the semiconductor substrate, the second semiconductor portion, and at least one spacer at least partially disposed between the first semiconductor portion and the second semiconductor portion. The semiconductor substrate and the first semiconductor portion respectively have a surface oriented on a first crystal plane, the second semiconductor portion has a surface oriented on a second crystal plane, wherein the first crystal plane is oriented differently than the second crystal plane.Type: GrantFiled: April 12, 2017Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang