Patents Examined by Dung Le
  • Patent number: 11233072
    Abstract: An array substrate, a display panel and a method for manufacturing the array substrate are provided. The array substrate further includes a first via and a second via. A conductive layer fills the first via and the second via to electrically connect the first metal layer and the second metal layer. The first via is disposed on a side of the second via, and a passivation layer partially extends between the first via and the second via. The display panel includes the above-mentioned array substrate.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: January 25, 2022
    Inventor: Peipei Xu
  • Patent number: 11233071
    Abstract: An electrode structure which includes a copper metal layer formed on a substrate, wherein the copper metal layer doped with a first metal ion within a first depth from upper surface, the first metal ion and the copper grain forming a copper alloy layer; the first depth being less than thickness of the copper metal layer, and the first metal ion being a metal ion having corrosion resistance and an ionic radius smaller than a gap between copper grains.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: January 25, 2022
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Xiaobo Hu
  • Patent number: 11233008
    Abstract: A method of manufacturing an integrated circuit having buried power rails includes forming a first dielectric layer on an upper surface of a first semiconductor substrate, forming a series of power rail trenches in an upper surface of the first dielectric layer, forming the buried power rails in the series of power rail trenches, forming a second dielectric layer on the upper surface of the first dielectric layer and upper surfaces of the buried power rails, forming a third dielectric layer on a donor wafer, bonding the third dielectric layer to the second dielectric layer, and forming a series of semiconductor devices, vias, and metal interconnects on or in the donor wafer. The buried power rails are encapsulated by the first dielectric layer and the second dielectric layer, and the buried power rails are below the plurality of semiconductor devices.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: January 25, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon Goo Hong, Kang-ill Seo, Mark S. Rodder
  • Patent number: 11222993
    Abstract: Methods and a device for cascading broadband emission are described. An example device can comprise a substrate, a bottom contact layer above at least a portion of the substrate, and a plurality of emission regions above the bottom contact layer. The plurality of emission regions can be disposed one above another. Each of the plurality of emission regions can be configured with different respective band gaps to emit radiation of different wavelengths. The device can comprise a plurality of tunnel junctions. Each of the tunnel junctions can be disposed between at least two corresponding emission regions of the plurality of emission regions. The device can comprise a top contact layer above the plurality of emission regions.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: January 11, 2022
    Assignee: UNIVERSITY OF IOWA RESEARCH FOUNDATION
    Inventors: John P. Prineas, Dennis Norton, Thomas F. Boggess, Russell J. Ricker
  • Patent number: 11217558
    Abstract: A method and a device for establishing a wire connection between a first contact surface and at least one further contact surface. A contact end of a wire is positioned in a contact position relative to the first contact surface with a wire guiding tool. Subsequently, a mechanical, electrically conductive connection is established between the first contact surface and the contact end with a first solder material connection, and subsequently the wire guiding tool is moved to the further contact surface thus forming a wire section and establishing a further mechanical, electrically conductive connection between the wire section end and the further contact surface with a further solder material connection.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: January 4, 2022
    Assignee: PAC TECH—PACKAGING TECHNOLOGIES GMBH
    Inventors: Andrej Kolbasow, Jan Hoffmann, Matthias Fettke
  • Patent number: 11211570
    Abstract: Hole transporting material obtained through a process comprising: reacting at least one heteropoly acid containing at least one transition metal belonging to group 5 or 6 of the Periodic Table of the Elements; with an equivalent amount of at least one salt or one complex of a transition metal belonging to group 5 or 6 of the Periodic Table of the Elements with an organic anion, or with an organic ligand; in the presence of at least one organic solvent selected from alcohols, ketones, esters. Said hole transporting material can be advantageously used in the construction of photovoltaic devices (or solar devices) such as, for example, photovoltaic cells (or solar cells), photovoltaic modules (or solar modules), either on a rigid support, or on a flexible support. Furthermore, said hole transporting material can be advantageously used in the construction of Organic Light Emitting Diodes (OLEDs), or of Organic Field Effect Transistors (OFETs).
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: December 28, 2021
    Assignee: ENI S.P.A.
    Inventors: Riccardo Po′, Alessandra Cominetti
  • Patent number: 11209323
    Abstract: In some embodiments, a sensor package includes: a substrate including a sensing area; a terminal portion disposed on a side of the sensing area of the substrate and including at least one terminal connected to the outside; a first outer wall disposed on the substrate and including a main wall surrounding at least some outer portions of the sensing area; at least one wire patterned and disposed on the substrate and configured to connect the sensing area and the terminal portion to each other; and a cover disposed on the first outer wall to correspond to the sensing area. Part of the main wall is disposed between the sensing area and the terminal portion, and the main wall includes an opening through which the at least one wire passes. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: December 28, 2021
    Assignee: HAESUNG DS CO., LTD.
    Inventor: Jin Woo Lee
  • Patent number: 11205753
    Abstract: Provided herein is a sequentially processed fabrication method involving donor-acceptor conjugated polymers with temperature dependent aggregation (TDA) useful for the preparation of organic semiconductors with improved properties.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: December 21, 2021
    Assignee: The Hong Kong University of Science and Technology
    Inventors: He Yan, Guangye Zhang
  • Patent number: 11201065
    Abstract: A method of manufacturing a semiconductor package includes covering a semiconductor die and a plurality of conductive terminals coupled to the semiconductor die in a mold compound, positioning the mold compound between a first pair of electrodes and a second pair of electrodes, and moving a movable electrode of the first pair and a movable electrode of the second pair into a first clamping position. In the first clamping position, each of the first pair of electrodes and the second pair of electrodes electrically couples to a unique subset of the plurality of conductive terminals. The method also includes applying, by the first pair of electrodes, a first voltage to the semiconductor die within the mold compound; and applying, by the second pair of electrodes, a second voltage to the semiconductor die within the mold compound. The second voltage is less than the first voltage.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: December 14, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Enis Tuncer, Byron Harry Gibbs
  • Patent number: 11201294
    Abstract: The invention provides a photoelectric conversion element exhibiting excellent photoelectric conversion efficiency even in a case where the photoelectric conversion film is a thin film. Also, the invention provides an optical sensor and an imaging element including the photoelectric conversion element. The invention provides a compound applied to the photoelectric conversion element. The photoelectric conversion element of the invention includes a conductive film, a photoelectric conversion film, and a transparent conductive film, in this order, in which the photoelectric conversion film contains a compound represented by Formula (1).
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: December 14, 2021
    Assignee: FUJIFILM Corporation
    Inventors: Eiji Fukuzaki, Tomoaki Yoshioka
  • Patent number: 11192901
    Abstract: A nitrogen-containing heterocyclic organic compound and an organic electroluminescent device are provided. The nitrogen-containing heterocyclic organic compound has a structure represented by the following general formula (I): and X is N or CH; Y is a single bond, O, S, an imino, a methylene, a methylidenesilane group, a substituted imino, a substituted methylene, or a substituted methylidenesilane group, the substituents in the substituted imino, and the substituted methylene; L, Ar1, and Ar2 are each independently selected from one of a C6-C30 aryl, a C3-C30 heteroaryl, a substituted C6-C30 aryl, and a substituted C3-C30 heteroaryl; n is an integer from 0 to 3; R1 to R8 are each independently selected from one of a hydrogen, a deuteron, a halogen, a C1-C30 alkyl, a C1-C30 alkyl substituted with a heteroatom, a C6-C30 aryl, and a C3-C30 heteroaryl.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: December 7, 2021
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Shipan Wang
  • Patent number: 11195768
    Abstract: A manufacturing method of a through electrode substrate includes: a step of preparing a substrate including a first surface and a second surface positioned oppositely to the first surface, and provided with a through hole; a step of providing a sealing layer blocking the through hole on the first surface of the substrate; an electrode forming step of forming a through electrode inside the through hole, the through electrode having a fist part extending along a sidewall of the through hole, and a second part connected to the first part and spreading along the sealing layer; and a step of removing the sealing layer.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: December 7, 2021
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Hiroshi Kudo, Takamasa Takano
  • Patent number: 11189664
    Abstract: A device for detecting an electromagnetic radiation has at least one photodetector including an organic diode and an organic photodiode formed in a same stack of semiconductor layers, the organic photodiode receiving the radiation. The photodetector further includes at least one screen which is opaque to the radiation and screens the portion of the stack corresponding to the diode.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: November 30, 2021
    Assignee: ISORG
    Inventors: Adrien Bailly, Emeline Saracco, Benjamin Bouthinon, Franck Hingant
  • Patent number: 11189803
    Abstract: An organic electroluminescence device includes an anode, an emitting layer, and a cathode. The emitting layer contains a first compound, a second compound, and a third compound. An ionization potential Ip1 of the first compound and an ionization potential Ip2 of the second compound satisfy the numerical expression. 0?Ip2?Ip1?0.8[eV] The first compound is a delayed fluorescent compound. The second compound is a fluorescent compound. The third compound has an electron mobility of 1×10?8 cm2/(V·s) or more.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: November 30, 2021
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Kei Yoshizaki, Toshinari Ogiwara
  • Patent number: 11189433
    Abstract: A multifunctional solid-state photovoltachromic device (1) comprising at least one n-type layer (8) and at least one p-type layer (11) arranged to create a PN or PIN junction, said n-type layer (8) and p-type layer (11) comprising materials arranged to act as mixed conductors, thus allowing both charge transport and ion conduction.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: November 30, 2021
    Assignee: CONSIGLIO NAZIONALE DELLE RICERCHE
    Inventors: Alessandro Cannavale, Pierluigi Cossari, Vincenzo Maiorano, Giuseppe Gigli
  • Patent number: 11191162
    Abstract: Provided is a circuit board supporting structure capable of easily detaching a circuit board on a base. The circuit board supporting structure is configured to support a circuit board on a base, in which the base has a concave portion formed in a placement surface of the circuit board, and a rotational operation member configured to be rotatably accommodated in the concave portion and extend and retract in a direction perpendicular to the placement surface by a rotational operation, in which the circuit board has a through hole formed at a position corresponding to the concave portion, in which the rotational operation member has a reference surface formed approximately in parallel with the placement surface, and an operation portion formed on a rotational axis of the rotational operation member so as to be exposed from the through hole.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: November 30, 2021
    Assignee: HOYA CORPORATION
    Inventor: Hiroaki Watanabe
  • Patent number: 11189802
    Abstract: There is provided an organic EL element having high efficiency and high driving stability despite having a low driving voltage.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: November 30, 2021
    Assignee: NIPPON STEEL CHEMICAL & MATERIAL CO., LTD.
    Inventors: Junya Ogawa, Masashi Tada
  • Patent number: 11183614
    Abstract: One embodiment discloses a semiconductor device comprising: a semiconductor structure, which comprises a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer arranged between the first conductive semiconductor layer and the second conductive semiconductor layer, and comprises a plurality of first recesses arranged up to a partial area of the first conductive semiconductor layer by penetrating the second conductive semiconductor layer and the active layer, and a second recess arranged between the plurality of first recesses; a plurality of first electrodes arranged inside the plurality of first recesses, and electrically connected with the first conductive semiconductor layer; a plurality of second electrodes electrically connected to the second conductive semiconductor layer; and a reflective layer arranged inside the second recess, wherein the sum of the area of the plurality of first recesses and the area of the second recess is 60% or less of the maximum area i
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: November 23, 2021
    Assignee: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
    Inventor: Su Ik Park
  • Patent number: 11177207
    Abstract: A transistor includes a semiconductor substrate having a first terminal and a second terminal. An interconnect structure is formed on an upper surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and electrically conductive material. The electrically conductive material of the interconnect structure includes a pillar in electrical contact with the first terminal, a first runner electrically connected to the pillar, a tap interconnect in electrical contact with the second terminal, a second runner electrically connected to the tap interconnect, a shield structure positioned between the pillar and the tap interconnect, and a shield runner electrically connected to the shield structure, the shield runner overlying the second runner in a direction perpendicular to the upper surface of the semiconductor substrate.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: November 16, 2021
    Assignee: NXP USA, Inc.
    Inventors: Vikas Shilimkar, Kevin Kim, Charles John Lessard, Humayun Kabir
  • Patent number: 11177439
    Abstract: A method can comprise providing an ink comprising reactants, a complexing agent, and a solvent, depositing the ink onto a substrate to form a wet film, drying the wet film to form a precursor layer, and annealing the precursor layer to form a perovskite film. The reactants can comprise a first and a second cation, a first metal, and a first and a second anion, wherein the first and second cations are different from each other, and the first and second anions are different from each other. The complexing agent can comprise a heterocyclic donor material. The perovskite film can comprise a mixed-cation mixed-halide perovskite material, and less than 5% by mass of the complexing agent. The perovskite film can also be formed using a one-step process.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: November 16, 2021
    Assignee: Tandem PV, Inc.
    Inventors: Colin David Bailie, Chris Eberspacher, Matthew Cornyn Kuchta