Abstract: A method of treating a semiconductor substrate includes converting a first main side of the semiconductor substrate having a first coefficient of static friction relative to a surface of a wafer table to a second coefficient of static friction relative to the surface of the wafer table, wherein the second coefficient of static friction is less than the first coefficient of static friction. A photoresist layer is applied over a second main side of the semiconductor substrate having the first coefficient of static friction. The second main side opposes the first main side. The semiconductor substrate is placed on the wafer table so that the first main side of the semiconductor substrate faces the wafer table.

Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with silicon nitride. The silicon nitride situated above the first region is doped by ion implantation. Trenches are etched through the silicon nitride and the doped silicon nitride is partially etching in an isotropic manner. The trenches are filled with an insulator to a level situated above that of the first region. The silicon nitride is removed resulting in the edges of the first region only being covered with an insulator annulus.

Abstract: A display substrate is provided. The display substrate includes: a plurality of pixel unit groups arranged in rows, each of the pixel unit groups including: a first-color sub-pixel unit, and a ring-shaped second-color sub-pixel unit surrounding the first-color sub-pixel unit.

Abstract: The present disclosure generally relates to display technology. A flexible display panel may include a flexible substrate; a display layer on the flexible substrate; and a lens layer and a color filter on the display layer. The display layer may include a plurality of light-emitting units. The color filter layer may include a black matrix that defines a plurality of filter units, each filter unit corresponding to one of the plurality of light-emitting units. The lens layer may include at least one lens that corresponds to at least one of the plurality of filter units, and that is configured to magnify light emitted by a light-emitting unit into a magnified light spot, and project the magnified light spot onto a filter unit corresponding to the light-emitting unit, the magnified light spot having an area larger than a surface area of the corresponding filter unit in a non-stretched state.

Abstract: An oxygen concentration is lowered in accordance with a set lowering process, and thereafter a heat treatment is performed. Accordingly, the heat treatment is performed to a substrate W while the oxygen concentration in a heat treating space HS is lowered. Consequently, a treatment atmosphere within the heat treating space is able to be made suitable for a heat treatment process, leading to appropriate film deposition. In addition, the oxygen concentration is lowered in accordance with a concentration level in recipes. This avoids an excessively lowered oxygen concentration, leading to prevention of reduced throughput.

Abstract: In a method of manufacturing a non-volatile memory device, insulating layers and conductive gates may be alternately formed on a semiconductor substrate to form a stack structure. A contact hole may be formed through the stack structure. A channel layer may be formed on a surface of the contact hole. The contact hole may be filled with a gap-fill insulating layer. The gap-fill insulating layer may be etched by a target depth to define a preliminary junction region. The channel layer may be etched until a surface of the channel layer may correspond to a surface of an uppermost gate among the gates. Diffusion-preventing ions may be implanted into the channel layer. A capping layer with impurities may be formed in the preliminary junction region.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack structure of a quantum dot device, wherein the quantum well stack structure includes an insulating material to define multiple rows of quantum dot formation regions; and a gate that extends over multiple ones of the rows.

Abstract: A wire substrate, a display device including a wire substrate, and a method of fabricating a wire substrate are disclosed. The display device comprises: a first base; and a first wiring layer disposed on the first base and comprising a conductive layer and a metal oxide layer stacked on the conductive layer, wherein the metal oxide layer comprises molybdenum (Mo), tantalum (Ta), and oxygen (O). The conductive layer includes a first metal layer on the first base, and a second metal layer between the first metal layer and the metal oxide layer. The second metal layer has a higher electrical conductivity than the first metal layer, and a thickness of the second metal layer is greater than a thickness of the first metal layer.

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.

Abstract: Provided is a semiconductor package system. The system includes a substrate, a first semiconductor package on the substrate, a second semiconductor package on the substrate, a first passive element on the substrate, a heat dissipation structure on the first semiconductor package, the second semiconductor package, and the first passive element, and a first heat conduction layer between the first semiconductor package and the heat dissipation structure. A sum of a height of the first semiconductor package and a thickness of the first heat conduction layer may be greater than a height of the first passive element. The height of the first semiconductor package may be greater than a height of the second semiconductor package.

Abstract: A flash includes a substrate comprising an active region and two electron storage structures disposed at two sides of the active region, wherein each of the electron storage structures comprises a silicon oxide/silicon nitride/silicon oxide composite layer. A buried gate is embedded in the active region, wherein the buried gate only consists of a control gate and a gate dielectric layer, and the gate dielectric layer is formed by a single material. Two source/drain doping regions are disposed in the active region at two sides of the buried gate.

Abstract: A warpage reduction device the present disclosure includes a jig having a warped shape capable of distributing stress of a workpiece, a light source heating the workpiece so as to be flat, a pressurizer applying pressure to the heated workpiece to be pressed against the jig so as to be deformed, a cooler cooling the deformed workpiece, and a controller controlling operations of the light source, the pressurizer, and the cooler.

Abstract: A display device includes: a first base layer; a circuit element layer on the first base layer; a pixel definition layer on the circuit element layer and comprising a plurality of light-emitting openings which are spaced apart from each other and define a plurality of light-emitting regions; a second base layer spaced apart from and facing the first base layer; a light-shielding layer on the second base layer and comprising a plurality of openings respectively overlapping the light-emitting regions, wherein on a plane of the first base layer, shapes of first to third openings along one direction among the openings are different from each other.

Abstract: A display unit includes a first substrate, a transistor, first and second wiring layers, and an insulating film. The first substrate is provided with a display region and a peripheral region. The transistor is provided in the display region, and includes a semiconductor layer, a gate electrode facing the semiconductor layer, a gate insulating film between the gate electrode and the semiconductor layer, and a source-drain electrode electrically coupled to the semiconductor layer. The first wiring layer is provided in the peripheral region, electrically coupled to the transistor, and disposed closer to the first substrate than the same layer as the gate electrode and the source-drain electrode. The second wiring layer is provided on the first substrate and has an electric potential different from the first wiring layer. The insulating film is provided between the second wiring layer and the first wiring layer.

Abstract: Apparatus and method for monitoring wafer charges are proposed. A conductive pin, a conductive spring and a conductive line are configured in series to connect the backside surface of the wafer and the sample conductor so that the backside surface of the wafer and the surface of the sample conductor have identical charge density. Hence, by using a static electricity sensor positioned close to the surface of the sample conductor, the charges on the wafer may be monitored. Note that the charges appeared on the frontside surface of the wafer induces charges on the backside surface of the wafer. The sample conductor is a sheet conductor and properly insulated from the surrounding environment. As usual, the sample conductor and the static electricity sensor are positioned outside the chamber where the wafer is placed and processed, so as to simplify the apparatus inside the chamber and reduce the contamination risk.

Abstract: A method for fabricating quantum rods includes: preparing a Cd-precursor; preparing a S-precursor and CdSe seeds; preparing a Zn-precursor; mixing the S-precursor and the CdSe seeds with the Cd-precursor in a reaction mixture; adding the Zn-precursor to the reaction mixture; stopping the reaction; and performing a purification process to obtain the quantum rods.

Abstract: A method of manufacturing an electronic device. For example and without limitation, various aspects of the present disclosure provide a method of manufacturing an electronic device that comprises a die comprising a circuit side and a second die side opposite the circuit side, a through hole in the die that extends between the second side of the die and the circuit side of the die, an insulating layer coupled to the inner wall of the through hole, a through electrode inside of the insulating layer, a dielectric layer coupled to the second side of the die, and a conductive pad coupled to the through electrode. The through electrode and the insulating layer may, for example, extend substantially the same distance from the second side of the die.

Abstract: A dummy gate layer is formed over a substrate. A patterned mask is formed over the dummy gate layer. The patterned mask includes an opening. The opening is etched into the dummy gate layer. The patterned mask serves as a protective mask as the opening is etched. A lateral etching process is performed to portions of the dummy gate layer laterally exposed by the opening. The lateral etching process etches away the dummy gate layer without substantially affecting the patterned mask. After the lateral etching process is performed, a dielectric material is formed in the opening. An air gap is formed in the dielectric material. After the air gap is formed, the patterned mask and portions of the dielectric material formed over the patterned mask are removed. The dummy gate layer is replaced with a metal-containing gate.

Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.

Abstract: A light emitting diode module comprising: at least one light emitting diode structure, an integrated reflector arrangement that comprises a reflector surface for reflecting light from a light emitting area of the light emitting diode structure. The integrated reflector arrangement further comprises a back reflection surface for diffusely reflecting light emitted via a side surface of the light emitting diode structure back to the light emitting diode structure. The back reflection surface is directly attached to at least a part of the side surface such that during operation of the light emitting diode module an emission of stray light by means of the side surface is reduced. The invention finally describes a flash module, an automotive front lighting or a projection light emitting diode system comprising at least one light emitting diode module.