Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region. A first electrode layer is formed overlying the surface region. A copper layer is formed overlying the first electrode layer and an indium layer is formed overlying the copper layer to form a multi-layered structure. The method subject at least the multi-layered structure to a thermal treatment process in an environment containing a sulfur bearing species to form a bulk copper indium disulfide material. The bulk copper indium disulfide material includes one or more portions of copper indium disulfide material characterized by a copper-to-indium atomic ratio of less than about 0.95:1 and a copper poor surface comprising a copper to indium atomic ratio of less than about 0.95:1.

Abstract: A method for forming a thin film photovoltaic device is provided. The method includes providing a transparent substrate comprising a surface region. A first electrode layer is formed overlying the surface region. A chalcopyrite material is formed overlying the first electrode layer. In a specific embodiment, the chalcopyrite material comprises a copper poor copper indium disulfide region. The copper poor copper indium disulfide region having an atomic ratio of Cu:In of about 0.95 and less. The method includes compensating the copper poor copper indium disulfide region using a sodium species to cause the chalcopyrite material to change from an n-type characteristic to a p-type characteristic. The method includes forming a window layer overlying the chalcopyrite material and forming a second electrode layer overlying the window layer.

Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region, forming a first electrode layer overlying the surface region, forming a copper layer overlying the first electrode layer and forming an indium layer overlying the copper layer to form a multi-layered structure. The multi-layered structure is subjected to a thermal treatment process in an environment containing a sulfur bearing species to forming a copper indium disulfide material. The copper indium disulfide material comprising a copper-to-indium atomic ratio ranging from about 1.2:1 to about 2:1 and a thickness of substantially copper sulfide material having a copper sulfide surface region. The thickness of the copper sulfide material is selectively removed to expose a surface region having a copper poor surface comprising a copper to indium atomic ratio of less than about 0.95:1.

Abstract: A method for forming a dual damascene pattern includes preparing a multi-functional hard mask composition including a silicon resin as a base resin, wherein the silicon resin comprises about 20 to 45% silicon molecules by weight, based on a total weight of the resin; forming a deposition structure by sequentially forming a self-arrangement contact (SAC) insulating film, a first dielectric film, an etching barrier film, and a second dielectric film over a hardwiring layer; etching the deposition structure to expose the hardwiring layer, thereby forming a via hole; coating the multi-functional hard mask composition over the second dielectric film and in the via hole to form a multi-functional hard mask film; and etching the resulting structure to expose a part of the first dielectric film using a photoresist pattern as an etching mask, thereby forming a trench having a width greater than that of the via hole.

Abstract: Provided is an image sensor. The image sensor includes a semiconductor substrate, photodiode structures, color filters, and microlenses. The semiconductor substrate includes a first region having pixel regions and a second region around the first region. The pixel regions are arranged in a matrix configuration. Each of the photodiode structures has a photodiode in each of the pixel regions. The color filters are disposed on or over the photodiode structures, the color filters correspond to the pixel regions, respectively, and have different areas corresponding to incident angles of light.

Abstract: There is provided a semiconductor light-emitting device including a semiconductor light-emitting element, a phosphor layer disposed in a light path of a light emitted from the semiconductor light-emitting element, containing a phosphor to be excited by the light and having a cross-section in a region of a diameter which is 1 mm larger than that of a cross-section of the light path, and a heat-releasing member disposed in contact with at least a portion of the phosphor layer and exhibiting a higher thermal conductance than that of the phosphor layer.

Abstract: A method of attaching a solder ball to a bonding pad includes disposing flux on the bonding pad, attaching a conductive metal ring to the pad using the flux, and placing the solder ball in the ring. A reflow operation is performed that secures the ring to the pad and melts the solder ball into and around the ring. A solder joint is formed between solder ball and the pad, with the ring secured within the ball. Use of the ring allows for higher stand-off height to be achieved with similar solder ball size, without having to use bigger ball size as in the conventional method, which causes solder ball bridging. With higher stand-off height, better board level reliability performance can be obtained.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed between a gate electrode and an outer portion of an active region of a FET. Also provided is a structure having a high-leakage dielectric formed between the gate electrode and the active region of the FET and a method of manufacturing such structure.

Abstract: A light-emitting device of the present invention includes: a LED chip 10; a chip mounting member 70 having a conductive plate (heat transfer plate) 71 one surface side of which the LED chip 10 is mounted on and a conductor patterns 73, 73 which is formed on the one surface side of the conductive plate 71 through an insulating part 72 and electrically connected to the LED chip 10; and a sheet-shaped connecting member 80 disposed on the other surface side of the conductive plate 71 to connect the conductive plate 71 to a body of the luminaire 90 which is a metal member for holding the chip mounting member 70. The connecting member 80 is made of a resin sheet which includes a filler and whose viscosity is reduced by heating, and the connecting member 80 has an electrical insulating property and thermally connects the conductive plate 71 and the body 90 of the luminaire to each other.

Abstract: A circuit for protecting a transistor during the manufacture of an integrated circuit device is disclosed. The circuit comprises a transistor having a gate formed over an active region formed in a die of the integrated circuit device; a protection element formed in the die of the integrated circuit device; and a programmable interconnect coupled between the gate of the transistor and the protection element, the programmable interconnect enabling the protection element to be decoupled from the transistor.

Abstract: A semiconductor device of one embodiment of the present invention includes a substrate; isolation layers, each of which is formed in a trench formed on the substrate and has an insulating film and a conductive layer; a semiconductor layer of a first conductivity type for storing signal charges, formed between the isolation layers and isolated from the conductive layers by the insulating films; a semiconductor layer of a second conductivity type, formed under the semiconductor layer of the first conductivity type; and a transistor having a gate insulator film formed on the semiconductor layer of the first conductivity type and a gate electrode formed on the gate insulator film.

Abstract: A method of laser machining a feature in a substrate includes machining the substrate with a pulsed laser along a scan line so that the successive pulses 81 at the substrate do not overlap but are either contiguous or spaced apart. Pulses 82, 83, 84 in respective succeeding scans of the laser along the scan line, are offset with respect to the starting point of pulses 81, 82, 83 in a previous scan so that multiple successive laser scans provide machining to a required depth while successively smoothing edges, 91, 92, 93, 94 of the feature with each pass.

Abstract: A coating composition and related coated substrates are disclosed. The coating composition of the present invention includes a first dielectric layer having a thickness ranging from 380 ? to 430 ?; a first metal layer over the first dielectric layer having a thickness ranging from 60 ? to 130 ?; a first primer layer over the first dielectric layer having a thickness ranging from 10 ? to 30 ?; a second dielectric layer over the first primer layer having a thickness ranging from 880 ? to 1020 ?; a second metal layer over the second dielectric layer having a thickness ranging from 100 ? to 180 ?; a second primer layer over the second metal layer having a thickness ranging from 10 ? to 30 ?; and a third dielectric layer over the second primer layer having a thickness ranging from 240 ? to 520 ?.

Abstract: A device for emitting various colors by mixing light from a first light emitting diode and light from a second light emitting diode comprises, according to one embodiment: the first light emitting diode including an LED chip comprising InGaN and being capable of emitting a blue color light, and a phosphor capable of absorbing a part of the blue color light and emitting a yellow color light, the blue color light and the yellow color light being mixed to make white-color light; the second light emitting diode being capable of emitting red, green or blue color light; and a drive circuit for separately driving each of the first and second light emitting diode.

Abstract: It is provided a contacting method when a plurality of films to be peeled are laminating. Reduction of total layout area, miniaturization of a module, weight reduction, thinning, narrowing a frame of a display device, or the like can be realized by sequentially laminating a plurality of films to be peeled which are once separately formed over a plastic film or the like. Moreover, reliable contact having high degree of freedom is realized by forming each layer having a connection face of a conductive material and by patterning with the use of a photomask having the same pattern.

Abstract: A pixel structure driven by a scan line and a data line arranged on a substrate is provided. The pixel structure includes a control unit, an OEL unit and a semi-transparent reflector structure. The control unit driven by the scan line and the data line is arranged on the substrate. The OEL unit is arranged on the substrate and includes a transparent electrode, a light-emitting layer and a metal electrode. The transparent electrode is electrically connected with the control unit. The light-emitting layer is disposed on the transparent electrode. The metal electrode is disposed on the light-emitting layer. The semi-transparent reflector structure is sandwiched between the substrate and the OEL unit, and includes at least a plurality of first and second dielectric layers. The first and second dielectric layers are alternately stacked, and the refractive index of the first dielectric layers is different from that of the second dielectric layers.

Abstract: A fabricating method of a polysilicon layer is disclosed which can be applied for fabricating a semiconductor device such as a SRAM and so on. The method for fabricating the semiconductor device includes the steps of: forming a transistor included in the semiconductor device on a semi conductor substrate forming an insulating layer on the transistor; forming contact holes, through which a region of the transistor is exposed, by selectively removing the insulating layer forming a silicon layer in the contact holes forming a metal layer on the insulating layer and the silicon layer; forming a metal suicide layer through heat treatment of the silicon layer and the metal layer; removing the metal layer; forming an amorphous silicon layer on the insulating layer and the metal suicide layer; and forming a polysilicon layer through heat treatment of the amorphous silicon layer.

Abstract: A lower electrode film is formed above a semiconductor substrate first, and then a ferroelectric film is formed on the lower electrode film. After that, an upper electrode film is formed on the ferroelectric film. When forming the upper electrode, an IrOx film containing crystallized small crystals when formed is formed on the ferroelectric film first, and then an IrOx film containing columnar crystals is formed.

Abstract: The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.

Abstract: The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.