Abstract: A method of forming a semiconductor device includes forming a first redistribution line on a substrate; forming a plurality of first vertical conductive structures on the first redistribution line and electrically coupled to the first redistribution line; forming a plurality of second vertical conductive structures on the substrate, wherein the first vertical conductive structures and the second vertical conductive structures are interlaced with each other, and the second vertical conductive structures are spaced apart from the first redistribution line; attaching a device die on the substrate; applying a molding compound in a molding layer overlying the substrate to surround the device die; and forming a second redistribution line on the molding layer, wherein the second redistribution line is electrically coupled to the second vertical conductive structures.

Abstract: A display device according to the present invention includes a display region arranged with a plurality of pixels, and a sealing layer covering the display region, wherein the sealing layer includes an insulation layer having a density pattern, the density pattern is a pattern including a low density region and a high density region, the low density region has the insulation layer with a lower density than an average density within the display region of the insulation layer, and the high density region has the insulation layer with a higher density than an average density within the display region of the insulation layer.

Abstract: A thin film transistor, a method for manufacturing the same, an array substrate and a display device are disclosed. The thin film transistor includes a gate having a gate metal layer on a surface of a substrate; a gate insulating layer on the substrate and covering the gate; an active layer on a surface of the gate insulating layer away from the substrate; a source comprising a source metal layer on a surface of the active layer away from the substrate; and a drain having a drain metal layer on a surface of the active layer away from the substrate, wherein the gate, the source or the drain further includes a metal complex layer on a surface of the gate metal layer, the source metal layer or the drain metal layer away from the substrate.

Abstract: A method includes performing an ion beam etching process on a tunnel magnetoresistance (TMR) stack to remove material portions of a first magnetic layer and a tunnel barrier layer of the TMR stack. The ion beam etching process stops at a top surface of a second magnetic layer of the TMR stack. A protective layer is deposited over the TMR stack. Another etch process is performed to remove the protective layer such that a portion of the second magnetic layer is exposed from the protective layer and a spacer is formed from a remaining portion of the protective layer. The spacer surrounds sidewalls of the first magnetic layer and the tunnel barrier layer. The portion of the second magnetic layer exposed from the protective layer is removed so that a TMR sensor element remains, where the TMR sensor element includes a bottom magnet, a top magnet, and a tunnel junction.

Abstract: A semiconductor package may include a first chip stack including first chips which are stacked on a package substrate. The semiconductor package may include a second chip stack including second chips which are stacked on the package substrate. The semiconductor package may include a third chip disposed on the first and second chip stacks.

Abstract: A light emitting device package includes: a plurality of light emitting chips configured to emit respective wavelength lights, each chip comprising electrodes at a bottom of the chip to form a flip-chip structure; a plurality of wirings directly connected to the electrodes of the chips, respectively; a plurality of electrode pads disposed below the chips and directly connected to the wirings, respectively; and a molding member integrally formed in a single layer structure to cover upper surfaces and side surfaces of the chips, and including a translucent material having a predetermined transmittance, wherein the wirings are disposed below a lower surface of the molding member.

Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die, a multilayer redistribution structure, a first mold compound, and a second mold compound. The first thinned die includes a first device layer formed from glass materials. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.

Abstract: A semiconductor device having stable electrical characteristics is provided. Alternatively, a highly reliable semiconductor device suitable for miniaturization or high integration is provided. The semiconductor device includes a first barrier layer, a second barrier layer, a third barrier layer, a transistor including an oxide, an insulator, and a conductor. The insulator includes an oxygen-excess region. The insulator and the oxide are between the first barrier layer and the second barrier layer. The conductor is in an opening of the first barrier layer, an opening of the second barrier layer, and an opening of the insulator with the third barrier layer positioned therebetween.

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

Abstract: Disclosed is a light emitting device and a method of manufacturing the same. The light emitting device includes a body, a first electrode installed in the body and a second electrode separated from the first electrode, a light emitting chip formed on one of the first and second electrodes, and electrically connected to the first and second electrodes, and a protective cap projecting between the first and second electrodes.

Abstract: Airtightness of a hollow portion is maintained, and yield and durability are improved. A semiconductor device 1 includes a device substrate 2, a semiconductor circuit 3, a sealing frame 7, a cap substrate 8, via portions 10, electrodes 11, 12 and 13, and a bump portion 14 or the like. A hollow portion 9 in which the semiconductor circuit 3 is housed in an airtight state is provided between the device substrate 2 and the cap substrate 8. The bump portion 14 connects all the via portions 10 and the cap substrate 8. Thus, the via portions 10 can be reinforced using the bump portion 14A.

Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.

Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die, a multilayer redistribution structure, a first mold compound, and a second mold compound. The first thinned die includes a first device layer formed from glass materials. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate having a first side and a second side opposite to the first side; an interconnect structure disposed on the first side, the interconnect structure including a dielectric layer, and a first conductive member and a second conductive member within the dielectric layer; a waveguide disposed between the first conductive member and the second conductive member within the dielectric layer, the waveguide including a first waveguide layer, a second waveguide layer and an adhesive layer between the first waveguide layer and the second waveguide layer; a first die disposed at the first side and over the interconnect structure and electrically connected to the first conductive member; and a second die disposed at the first side and over the interconnect structure and electrically connected to the second conductive member. An associated method for fabricating the same is also disclosed.

Abstract: A method of manufacturing a three-dimensional (3D) stacked semiconductor structure is provided. A multi-layered stack is formed above a substrate, and the multi-layered stack comprises a plurality of nitride layers and polysilicon layers arranged alternately. Several channel holes are formed vertically to the substrate. The multi-layered stack is patterned to form linear spaces between the channel holes, wherein the linear spaces extend downwardly for being vertical to the substrate and to expose sidewalls of the nitride layers and the polysilicon layers. Then, the polysilicon layers are replaced with insulating layers having air-gaps through the linear spaces, and the nitride layers are replaced with conductive layers through the linear spaces.

Abstract: A light-emitting device of the present invention includes: a LED chip 10; a chip mounting member 70 having a conductive plate (heat transfer plate) 71 one surface side of which the LED chip 10 is mounted on and a conductor patterns 73, 73 which is formed on the one surface side of the conductive plate 71 through an insulating part 72 and electrically connected to the LED chip 10; and a sheet-shaped connecting member 80 disposed on the other surface side of the conductive plate 71 to connect the conductive plate 71 to a body of the luminaire 90 which is a metal member for holding the chip mounting member 70. The connecting member 80 is made of a resin sheet which includes a filler and whose viscosity is reduced by heating, and the connecting member 80 has an electrical insulating property and thermally connects the conductive plate 71 and the body 90 of the luminaire to each other.

Abstract: The present invention relates to an integrated device, comprising a semiconductor device formed on a semiconductor substrate, a temperature sensing element formed within a semi-conductive layer formed on the semiconductor substrate, an electrically insulating layer formed over the semi-conductive layer, a metal layer formed over the insulation layer and forming an electrical contact of the semiconductor device, and a thermal contact extending from the metal layer through the electrically insulating layer to a first region of the semi-conductive layer, wherein the first region of the semi-conductive layer is electrically isolated from the temperature sensing element. The present invention also relates to a method of forming a temperature sensing element for integration with a semiconductor device.

Abstract: A semiconductor device includes a semiconductor substrate, a cell region, an outer peripheral region, a field plate, an outermost peripheral ring, outer peripheral region layer, an insulator film, and a Zener diode. The semiconductor substrate has a superjunction structure. The outer peripheral region is disposed at an outer periphery of the cell region. The Zener diode is disposed on the insulator film for electrically connecting the field plate with the outermost peripheral ring. The Zener diode has a first conductivity type region and a second conductivity type region that are alternately arranged in a direction from the cell region to the outer peripheral region.

Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region. A first electrode layer is formed overlying the surface region. A copper layer is formed overlying the first electrode layer and an indium layer is formed overlying the copper layer to form a multi-layered structure. The method subjects at least the multi-layered structure to a thermal treatment process in an environment containing a sulfur bearing species to form a bulk copper indium disulfide material. The bulk copper indium disulfide material comprises one or more portions of copper indium disulfide material and a copper poor surface region characterized by a copper-to-indium atomic ratio of less than about 0.95:1.

Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region. A first electrode layer is formed overlying the surface region. A copper layer is formed overlying the first electrode layer and an indium layer is formed overlying the copper layer to form a multi-layered structure. The method subject at least the multi-layered structure to a thermal treatment process in an environment containing a sulfur bearing species to form a bulk copper indium disulfide material. The bulk copper indium disulfide material includes one or more portions of copper indium disulfide material characterized by a copper-to-indium atomic ratio of less than about 0.95:1 and a copper poor surface comprising a copper to indium atomic ratio of less than about 0.95:1.