Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate having a semiconductor substrate and a plurality of fins on the semiconductor substrate; forming an isolation structure on the semiconductor substrate, between adjacent fins and with a top surface lower than the top surfaces of the fins; forming a gate structure across of the fins by covering portions of top and side surfaces of the fins; forming a sidewall material layer to cover the gate structure and the fins; etching the sidewall material layer to form gate sidewall spacers on side surfaces of the gate structure and shadowing sidewall spacers on portions of side surfaces of the fins adjacent to the isolation structure; and performing an ion implantation process on the fins using the gate sidewall spacers and the shadowing sidewall spacers as a mask to form lightly doped regions in the fins.

Abstract: A light-emitting device includes a light-emitting element and a light-transmissive member containing a phosphor, particles, and a matrix, the phosphor and the particles being dispersed in the matrix, the particles including at least one of surface-treated particles, particles coexisting with a dispersing agent, and surface-treated particles coexisting with a dispersing agent, the particles being dispersed as aggregates, the particles having an average particle diameter in a range of 1 nm to 8 nm, a content of the particles falling within a range of 0.01 parts by mass to less than 5 parts by mass relative to 100 parts by mass of the matrix, a content of the phosphor falling within a range of 100 parts by mass to 300 parts by mass relative to 100 parts by mass of the matrix.

Abstract: A micro-bonding structure including a substrate, a conductive pad, a bonding layer, a micro device, and a diffusive bonding portion is provided. The conductive pad is present on the substrate. The bonding layer is present on the conductive pad. The micro device is present on the bonding layer. The diffusive bonding portion is present between and electrically connected with the bonding layer and the conductive pad. The diffusive bonding portion consists of at least a part of elements from the bonding layer and at least a part of elements from the conductive pad. A plurality of voids are present between the bonding layer and the conductive pad, and one of the voids is bounded by the diffusive bonding portion and at least one of the conductive pad and the bonding layer.

Abstract: A display device is disclosed, which includes: a support layer including a first surface, a second surface and a first side wall, wherein the first surface and the second surface locate at two opposite sides of the support layer, the first side wall connects the first surface and the second surface, a first angle is included between the first surface and the first side wall, and a second angle is included between the second surface and the first side wall; an adhesion layer disposed on the support layer; a base layer disposed on the adhesion layer; and plural transistors disposed on the base layer, wherein the first angle and the second angle are greater than 0 degree and less than 180 degrees, and the first angle and the second angle are different. In addition, an electronic device including the aforesaid display device is also disclosed.

Abstract: A semiconductor structure is provided that includes a pFET gate-all-around nanosheet structure and an nFET gate-all-around nanosheet structure integrated together on the same substrate. The pFET gate-all-around nanosheet structure contains a nickel monosilicide gate electrode layer that does not introduce strain into each suspended semiconductor channel material nanosheet of a first vertical stack of suspended semiconductor channel material nanosheets. The nFET gate-all-around nanosheet structure contains a Ni3Si gate electrode layer that introduces strain into each suspended semiconductor channel material nanosheet of a second vertical stack of suspended semiconductor channel material nanosheets.

Abstract: A light emitting element-mounting substrate of the present disclosure includes a base body, a metal layer and a glass layer. The base body is formed of ceramics. The metal layer is disposed on the base body, and contains copper as a main component. The glass layer is disposed on the metal layer, has a white color tone and contains a compound including titanium and oxygen.

Abstract: Chip scale package such as a chip scale package having a chip integrated therein to provide an integrated chip scale package.

Abstract: An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask.

Abstract: Photovoltaic devices based on an Ag2ZnSn(S,Se)4 (AZTSSe) absorber and techniques for formation thereof are provided. In one aspect, a method for forming a photovoltaic device includes the steps of: coating a substrate with a conductive layer; contacting the substrate with an Ag source, a Zn source, a Sn source, and at least one of a S source and a Se source under conditions sufficient to form an absorber layer on the conductive layer having Ag, Zn, Sn, and at least one of S and Se; and annealing the absorber layer. Methods of doping the AZTSSe are provided. A photovoltaic device is also provided.

Abstract: An ESD protection apparatus includes first and second parasitic bipolar junction transistors having different majority carriers formed in a substrate and an ESD protection device having a grounding end and a connecting end connected to the first parasitic bipolar junction transistor. When an ESD voltage applied to the ESD protection apparatus is greater than a ground voltage, a first current is grounded by passing through one of a first assembled protecting circuit including the first parasitic bipolar junction transistor and the ESD protection device and a second assembled protecting circuit including the first and the second parasitic bipolar junction transistor; and when an ESD voltage applied to the ESD protection apparatus is less than a ground voltage, a second current coming from a ground is directed to a voltage source by passing through the other one of the first assembled protecting circuit and the second assembled protecting circuit.

Abstract: The present disclosure relates to a CMOS image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within a substrate and respectively comprising a photodiode. A back-side deep trench isolation (BDTI) structure is disposed between adjacent pixel regions, extending from a back-side of the substrate to a position within the substrate. The BDTI structure comprises a doped layer lining a sidewall surface of a deep trench and a dielectric fill layer filling a remaining space of the deep trench. By forming the disclosed BDTI structure that functions as a doped well and an isolation structure, the implantation processes from a front-side of the substrate is simplified, and thus the exposure resolution, the full well capacity of the photodiode, and the pinned voltage is improved.

Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided. The method includes providing a base substrate including a first region and a second region; and forming a first doped region in the first region, and a second doped region in the second region. The second doped region is doped with blocking ions. The method also includes forming a first metal layer on a surface of the first doped region and on a surface of the second doped region; and forming a second metal layer on a surface of the first metal layer. The second metal layer is made of a material different from the first metal layer. Further, the method includes forming a first metal silicide layer and a second metal silicide layer by performing an annealing process. The blocking ions block atoms of the second metal layer from diffusing into the second metal silicide layer.

Abstract: The disclosure is directed to gate all-around integrated circuit structures, finFETs having a dielectric isolation, and methods of forming the same. The gate all-around integrated circuit structure may include a first insulator region within a substrate; a pair of remnant liner stubs disposed within the first insulator region; a second insulator region laterally adjacent to the first insulator region within the substrate; a pair of fins over the first insulator region, each fin in the pair of fins including an inner sidewall facing the inner sidewall of an adjacent fin in the pair of fins and an outer sidewall opposite the inner sidewall; and a gate structure substantially surrounding an axial portion of the pair of fins and at least partially disposed over the first and second insulator regions, wherein each remnant liner stub is substantially aligned with the inner sidewall of a respective fin of the pair of fins.

Abstract: The present invention relates to an improvement to a current field effect transistor and trans-impedance MOS devices based on a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. The present invention further relates to a super-saturation current field effect transistor (xiFET), having a source, a drain, a diffusion, a first gate, and a second gate terminals, in which a source channel is defined between the source and diffusion terminals, a drain channel is defined between the drain and diffusion terminals. The first gate terminal is capacitively coupled to the source channel; and the second gate terminal is capacitively coupled to said drain channel. The diffusion terminal receives a current causing change in diffused charge density throughout said source and drain channel. The xiFET provides a fundamental building block for designing various analog circuits.

Abstract: A semiconductor device includes a plurality of redistribution layers, a dielectric layer, and a conductive structure. The redistribution layers are formed overlying a device die to provide an electrical connection between the device die and an external connector in a package. The dielectric layer is arranged between the redistribution layers to form a capacitor structure. The conductive structure is formed and coupled between the device die and the redistribution layers.

Abstract: A method of forming a resistive memory device includes forming an alternating stack of insulating layers and sacrificial material layers that extend along a first horizontal direction over a substrate, forming a laterally alternating sequence of vertical conductive lines and dielectric pillar structures that alternate along the first horizontal direction on sidewalls of the alternating stack, forming lateral recesses by removing the sacrificial material layers selective to the insulating layers, selectively growing resistive memory material portions from physically exposed surfaces of the vertical conductive lines in the lateral recesses, and forming electrically conductive layers over the resistive memory material portions in the lateral recesses.

Abstract: A semiconductor device including a substrate, a first doped region, a second doped region, a gate, and a gate dielectric layer is provided. The substrate has a first conductive type. The first doped region is formed in the substrate and has a second conductive type. The second doped region is formed in the substrate and has the second conductive type. The gate is formed on the substrate and is disposed between the first and second doped regions. The gate dielectric layer is formed on the substrate and is disposed between the gate and the substrate. The gate dielectric layer includes a first region and a second region. The depth of the first region is different from the depth of the second region.

Abstract: In pixels that are two-dimensionally arranged in a matrix fashion in the pixel array unit of a solid-state imaging element, a photoelectric conversion film having a light shielding film buried therein is formed and stacked on the light incident side of the photodiode. The present technique can be applied to a CMOS image sensor compatible with the global shutter system, for example.

Abstract: A negative capacitance device includes a semiconductor layer. An interfacial layer is disposed over the semiconductor layer. An amorphous dielectric layer is disposed over the interfacial layer. A ferroelectric layer is disposed over the amorphous dielectric layer. A metal gate electrode is disposed over the ferroelectric layer. At least one of the following is true: the interfacial layer is doped; the amorphous dielectric layer has a nitridized outer surface; a diffusion-barrier layer is disposed between the amorphous dielectric layer and the ferroelectric layer; or a seed layer is disposed between the amorphous dielectric layer and the ferroelectric layer.

Abstract: An integrated circuit (IC) package is disclosed that contains high density interconnects to connect multiple dies. The IC package includes an encapsulated layer, a first dielectric layer, and a second dielectric layer. The encapsulated layer forms the base of the IC package and includes the multiple dies. The first dielectric layer positioned between the encapsulated layer and the second layer. The first dielectric layer includes vias to connect to the input/output pads of active surfaces of the multiple dies. The second dielectric layer includes interconnect layers where at least one of the interconnect layers forms an electrical path to connect at least two of the multiple dies together. According to embodiments of the present disclosure, the IC package enables a high manufacturing yield due to large tolerances allowed for selection of dies. Embodiments of the present disclosure also increase an amount of input/output interconnection between multiple dies in the IC package.