Abstract: A three-dimensional (3D) nonvolatile memory includes a stacked structure that includes a plurality of conductive layers that alternate with and are spaced apart from each other by a plurality of interlayer insulating layers. The stacked structure includes a first cell region, a second cell region spaced apart from the first cell region, and a connection region between the first cell region and the second cell region. The connection region includes a first step portion that contacts the first cell region and has a stepped shape that descends in a direction approaching the second cell region, a second step portion that contacts the second cell region and has a stepped shape that descends in a direction approaching the first cell region, and a connection portion that connects the first cell region and the second cell region.

Abstract: The present invention relates to an improvement to a current field effect transistor and trans-impedance MOS devices based on a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. The present invention further relates to a super-saturation current field effect transistor (xiFET), having a source, a drain, a diffusion, a first gate, and a second gate terminals, in which a source channel is defined between the source and diffusion terminals, a drain channel is defined between the drain and diffusion terminals. The first gate terminal is capacitively coupled to the source channel; and the second gate terminal is capacitively coupled to said drain channel. The diffusion terminal receives a current causing change in diffused charge density throughout said source and drain channel. The xiFET provides a fundamental building block for designing various analog circuites.

Abstract: To provide a semiconductor device having improved reliability by relaxing the unevenness of the injection distribution of electrons and holes into a charge accumulation film attributable to the shape of the fin of a MONOS memory comprised of a fin transistor. Of a memory gate electrode configuring a memory cell formed above a fin, a portion contiguous to an ONO film that covers the upper surface of the fin and a portion contiguous to the ONO film that covers the side surface of the fin are made of electrode materials different in work function, respectively, and the boundary surface between them is located below the upper surface of the fin.

Abstract: A semiconductor heterostructure including a polarization doped region is described. The region can correspond to an active region of a device, such as an optoelectronic device. The region includes an n-type semiconductor side and a p-type semiconductor side and can include one or more quantum wells located there between. The n-type and/or p-type semiconductor side can be formed of a group III nitride including aluminum and indium, where a first molar fraction of aluminum nitride and a first molar fraction of indium nitride increase (for the n-type side) or decrease (for the p-type side) along a growth direction to create the n- and/or p-polarizations.

Abstract: A staggered memory cell architecture staggers memory cells on opposite sides of a shared bit line preserves memory cell density, while increasing the distance between such memory cells, thereby reducing the possibility of a disturb. In one implementation, the memory cells along a first side of a shared bit line are connected to a set of global word lines provided underneath the memory structure, while the memory cells on the other side of the shared bit line—which are staggered relative to the memory cells on the first side—are connected to global word lines above the memory structure.

Abstract: A method for producing optoelectronic conversion semiconductor chips and a composite of conversion semiconductor chips are disclosed. In an embodiment the method includes growing a semiconductor layer sequence on a growth substrate, applying an electric contact on to a rear side of the semiconductor layer sequence facing away from the growth substrate, thinning the growth substrate, after thinning, cutting the growth substrate at least to the semiconductor layer sequence thereby forming a first intermediate space, applying a conversion layer on to the thinned growth substrate and singulating at least the thinned growth substrate and the semiconductor layer sequence.

Abstract: A porous base substrate is infiltrated with a polymer material to form a hybrid substrate that combines the optical advantages of both. Prior to infiltration, the base substrate may exhibit relatively low optical transmittance. For example, the base substrate may be paper, textiles, aerogels, natural wood, or any other porous material. By infiltrating the base substrate with a polymer having a similar refractive index to that of the material of the base substrate, the transmittance can thus be improved, resulting in, for example, a transparent hybrid substrate that exhibits both relatively high optical haze and relatively high optical transmittance within the visible light spectrum. The hybrid substrate can thus serve as a base for fabricating electronic devices or can be coupled to electronic devices, especially optical devices that can take utilize the unique optical properties of the hybrid substrate.

Abstract: The present disclosure relates to an electronic device. The electronic device comprises a substrate, a micro-electromechanical systems (MEMS) device and an attachment element. The substrate defines an opening penetrating the substrate. The MEMS device has an active surface facing away from the substrate and a sensing region facing toward the opening. The attachment element is disposed on the substrate and surrounding the opening and the sensing region of the MEMS device.

Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die, a multilayer redistribution structure, a first mold compound, and a second mold compound. The first thinned die includes a first device layer formed from glass materials. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.

Abstract: A method for fabricating a dual trench structure. The method includes providing a wafer comprising a semiconductor layer including a top surface. The method includes providing charge compensation trenches and termination trenches open to the top surface that are formed in a single etch step but with different final shield oxide thicknesses. A first shield oxide layer of a first thickness is formed on the plurality of charge compensation surfaces and the termination trench surface, wherein the first thickness of the first shield oxide layer is sufficient to allow formation of voids through the charge compensation trenches. Poly-silicon is deposited to form the electrodes in the charge compensation trenches. An isolated poly-silicon etch and clean etch is performed in the termination trenches to expose the first shield oxide layer. A second shield oxide layer is deposited on the first shield oxide layer in the termination trenches.

Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A nitrogen-containing layer is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.

Abstract: A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. A trench structure separates the P-type doped region from the N-type doped region. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. The trench structure may include a textured surface for increased solar radiation collection. Among other advantages, the resulting structure increases efficiency by providing isolation between adjacent P-type and N-type doped regions, thereby preventing recombination in a space charge region where the doped regions would have touched.

Abstract: A semiconductor device includes a region of semiconductor material having first and second opposing major surfaces. A trench structure includes a trench extending into the region of semiconductor material from the first major surface, wherein the first major surface defines a first horizontal plane in a cross-sectional view. The trench structure further includes a conductive material disposed within the trench and separated from the region of semiconductor material by a dielectric region. A Schottky contact region is disposed adjacent the first major surface on opposing sides of the trench structure, the Schottky contact region having an upper surface residing on a second horizontal plane in the cross-sectional view. The dielectric region comprises an uppermost surface and configured such that a major portion of the uppermost surface is disposed above the first horizontal plane in the cross-sectional view. The structure and method provide a semiconductor device with improved performance (e.g.

Abstract: Disclosed is a light emitting device and a method of manufacturing the same. The light emitting device includes a body, a first electrode installed in the body and a second electrode separated from the first electrode, a light emitting chip formed on one of the first and second electrodes, and electrically connected to the first and second electrodes, and a protective cap projecting between the first and second electrodes.

Abstract: A micro-bonding structure including a substrate, a conductive pad, a bonding layer, a micro device, and a diffusive bonding portion is provided. The conductive pad is on the substrate. The bonding layer is on the conductive pad. A thickness of the bonding layer ranges from about 0.2 ?m to about 2 ?m. The micro device is on the bonding layer. The diffusive bonding portion is between and electrically connected with the bonding layer and the conductive pad. The diffusive bonding portion consists of at least a part of elements from the bonding layer and at least a part of elements from the conductive pad. A plurality of voids are between the bonding layer and the conductive pad, and one of the voids is bounded by the diffusive bonding portion and at least one of the conductive pad and the bonding layer.

Abstract: A method for forming a MRAM device free of seal ring peeling defect, and the resulting device, are provided. Embodiments include forming magnetic tunnel junction (MTJ) over a metallization layer in a seal ring region of an MRAM device; forming a metal filled via connecting the MTJ and the metallization layer; forming a tunnel junction via over the MTJ; and forming a top electrode over the tunnel junction via.

Abstract: A semiconductor device according to an embodiment includes a first electrode; a second electrode; a silicon carbide layer disposed between the first electrode and the second electrode; an n-type silicon carbide region disposed in the silicon carbide layer and having a first nitrogen concentration; a first p-type silicon carbide region disposed in the silicon carbide layer between the n-type silicon carbide region and the first electrode and having a second nitrogen concentration higher than the first nitrogen concentration; and a second p-type silicon carbide region disposed in the silicon carbide layer between the first p-type silicon carbide region and the first electrode, having a third nitrogen concentration higher than the second nitrogen concentration, and having a p-type impurity concentration higher than that of the first p-type silicon carbide region.

Abstract: Disclosed are methods for the surface cleaning and passivation of PV absorbers, such as CdTe substrates usable in solar cells, and devices made by such methods. In some embodiments, the method involves an anode layer ion source (ALIS) plasma discharge process to clean and oxidize a CdTe surface to produce a thin oxide layer between the CdTe layer and subsequent back contact layer(s).

Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die, a multilayer redistribution structure, a first mold compound, and a second mold compound. The first thinned die includes a first device layer formed from glass materials. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.

Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.