Abstract: A highly reliable semiconductor device having a contact hole with a sufficient area can be obtained. An interlevel insulating film is formed on a conductive region having a first width. A through hole which exposes the conductive region is formed at the interlevel insulating film. A coating film is formed on the interlevel insulating film. In the coating film, an opening having a second width larger than the first width is formed in a region located on the through hole. An interconnect line is formed in a region located on the opening. A conductor film for electrically connecting the conductive region and the interconnect line is generated within the through hole.

Abstract: A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following defining the gate conductor shapes. In one embodiment, a borderless contact is provided by forming an insulating layer on a substrate, providing a conductive layer on the insulating layer, providing a second insulating layer on the conductive layer, providing a third insulating layer on the second insulating layer, removing preselected portions of the second and third insulating layers, providing a damage preventing layer in those areas where the second and third insulating layers have been removed, removing preselected portions of the third insulating layer, removing the damage preventing layer, removing exposed portions of the conductive layer, and removing now exposed portions of the second insulating layer.

Abstract: A dual leadframe package. A chip including a first surface and a second surface is provided. A gate and a first source/drain region are located on the first surface, and a second source/drain region is located on the second surface. A first lead including a first innerlead and a first outerlead and a second lead including a second innerlead and a second outerlead are provided. The first innerlead is coupled to the first source/drain region, and the second innerlead is coupled to the gate. A conductive plate including a top surface and a bottom surface is provided, and the top surface is coupled to the second source/drain region. A packaging material seals the chip, the first innerlead, the outerlead and a portion of the conductive plate. The bottom surface, the first outerlead and the second outerlead are exposed.

Abstract: A source region 3 and a back-gate region 4 are alternately arranged along one side of a gate electrode 2 in a power MOSFET. The back-gate region 4 is formed so as not to substantially include the region immediately below the gate electrode 2. Thereby, it is possible to prevent a parasitic bipolar transistor from operating while controlling the increase of a channel resistance and thus, the breakdown resistance is improved.

Abstract: A flash memory structure and a method of fabricating the same are provided. The flash memory structure is formed with buried bit lines that are lower in resistance, are shallower in buried depth into the substrate, and have a larger punchthrough margin than the prior art. The flash memory structure is constructed on a semiconductor substrate. A tunneling oxide layer is formed over the substrate. A plurality of floating gates is formed at predefined locations over the tunneling oxide layer. A plurality of sidewall spacers is formed on the sidewalls of the floating gates. A plurality of selective polysilicon blocks is formed over the substrate, each being formed between one neighboring pair of the floating gates. An ion-implantation process is performed to dope an impurity element through these selective polysilicon blocks into the substrate to thereby form a plurality of impurity-doped regions in the substrate to serve as a plurality of buried bit line for the flash memory device.

Abstract: An image pixel sensor array. The image pixel sensor array includes a substrate. An interconnect structure is formed adjacent to the substrate. A plurality of image pixel sensors are formed adjacent to the interconnect structure. Each image pixel sensor includes a pixel electrode, and an I-layer formed adjacent to the pixel electrode. The I-layer includes a first surface adjacent to the pixel electrode, and a second surface opposite the first surface. The first surface includes a first surface area which is less than a second surface area of the second surface. The image pixel sensor array further includes an insulating material between each image pixel sensor, and a transparent electrode formed over the image pixel sensors. The transparent electrode electrically connects the image pixel sensors and the interconnect structure.

Abstract: A MOSFET device with buried contact structure on a semiconductor substrate has the following major elements with their relative locations. A gate insulator is on a portion of the substrate and a gate electrode is on the gate insulator. A gate sidewall structure is located on sidewalls of the gate electrode. Inside the substrate, a lightly doped source/drain region is under the gate sidewall structure, and a doped source/drain region is abutting the lightly doped source/drain region and located aside from a region under the gate sidewall structure. In addition, a doped buried contact region is also in the substrate next to the doped source/drain region. On the substrate, a silicon connection is located on a portion of the doped buried contact region, and a shielding block is on the doped buried contact region covering only a region uncovered by the silicon connection.

Abstract: A massive heat slug in thermally coupled to the top of an IGBT to act as a local thermal inertia element to absorb and store heat from the die during peak temperature rise and to return heat to the die at reduced die temperature, thereby reducing the ratio of die peak temperature to die average temperature. The device is useful in applications in which the IGBT is called upon to carry current at a range of frequencies which includes very low (eg 3 Hz) frequencies as in a motor control circuit.

Abstract: It is an object of the present invention to reduce the weight of a stage unit and suppress heat generation of the driving unit of the stage, thereby improving the surface accuracy of the stage or measurement precision of an interferometer for measuring the position of the stage. A reticle base, a scanning stage mounted on the reticle stage and moved in the scanning direction, and a fine adjustment stage mounted on the scanning stage and capable of being finely moved in the X and Y directions and in the rotational direction are provided as a reticle stage. A first electromagnetic actuator for performing driving in the scanning direction, and a second electromagnetic actuator, having a smaller thrust than that of the first electromagnetic actuator, for performing driving in a direction perpendicular to the scanning direction are provided as the driving unit of the fine adjustment stage.

Abstract: A semiconductor device includes a F-doped interlayer insulation film and a high-refractive index insulation film having a refractive index higher than a refractive index of the F-doped interlayer insulation film, such that the high-refractive index insulation film is disposed at least one of a top side and a bottom side of the F-doped interlayer insulation film.

Abstract: The semiconductor device includes and the method for fabricating the same forms a damaged region under a gate electrode to improve device performance and simplify the process. The semiconductor device includes a substrate in which a buried insulating layer is formed; device isolating layers buried in first predetermined areas of the substrate to contact with the buried insulating layer; a gate electrode formed over a second predetermined area of the substrate; sidewall spacers formed on both sides of the gate electrode; source and drain regions at both sides of the gate electrode; and the damaged region at boundary of the buried insulating layer under the gate electrode.

Abstract: A multi-level flash memory cell formed in a semiconductor substrate. The memory cell comprises: (a) a deep n-well formed in said semiconductor substrate; (b) a p-well formed within said deep n-well; (c) a first insulating layer formed over said p-well; (d) three floating gates adjacent to and insulated from one another and lying atop said first insulating layer; (e) source and drain regions formed in said p-well and on either side of said three floating gates; (f) a second insulating layer atop said three floating gates and said drain and source regions; and (g) a control gate formed atop said second insulating layer.

Abstract: A thin film transistor which can be used in an LCD display panel includes an insulator substrate, a gate electrode located on the insulator substrate, an insulator film provided on the insulator substrate and the gate electrode, and a polycrystalline silicon film located on the insulator film. A channel is defined in a first portion of the polycrystalline silicon film over the gate electrode, and a drain and a source are defined in second and third portions of the polycrystalline silicon film over the insulator substrate. Grain sizes of the drain and source are equal to or greater than a grain size of the channel.

Abstract: The semiconductor device comprises a base substrate, a wiring 54 formed on the base substrate, a first insulating film 48, 56 for covering the upper surface and the side surfaces of the wiring 54, an etching stopper film 58 formed on the base substrate and the first insulating film 48, 56, a conductor plug 36b connected to the base substrate through the etching stopper film 58 and projected upper of the base substrate, and a capacitor 79 having one electrode 68 connected to the upper surface and the side surfaces of the conductor plug 36b. The electrode 68 is formed not only on the upper surface of the conductor plug 36b but also on the side walls thereof, whereby the electrode 68 can be fixed to the conductor plug 36b without failure.

Abstract: A microelectronic component for mounting a rigid substrate, such as a hybrid circuit to a rigid support substrate, such as a printed circuit board. The microelectronic component includes a rigid interposer which may have a chip mounted on its first surface; a pattern of contacts on the rigid interposer; a flexible interposer overlying the second surface of the rigid interposer; a pattern of terminals on the flexible interposer; flexible leads; and solder coated copper balls mounted on the flexible interposer. The microelectronic component may have a socket assembly mounted on the first surface of the rigid interposer. The microelectronic component may be mounted on a rigid support substrate.

Abstract: A semiconductor device having a reduced resistance-capacitance time constant is formed by treating a dielectric layer to reduce its dielectric constant. Embodiments include exposing a deposited dielectric layer to ionic radiation, as with Helium ion implantation, to form voids within the layer, thereby reducing its dielectric constant.

Abstract: An improved RC network integrated circuit semiconductor device is disclosed which incorporates an improved method for fabrication. The new device and method includes the use of a tantalum nitride layer as the resistive material for the resistor and a protective metal layer formed between the resistive layer and a metal interconnect layer. The capacitor uses a metal electrode as one plate of the capacitor and a heavily doped semiconductor region as the other plate of the capacitor and separated from the one plate of the capacitor by a silicon nitride insulation layer.

Abstract: A circuit assembly includes a substrate layer, a first conductive layer mounted to the substrate layer and a second conductive layer. The first and second conductive layers are adhered by an adhesive layer having non-electrically conductive particles for separating the first and second conductive layers.

Abstract: The present invention provides an image forming apparatus for forming an image on a recording material having light interference in which a latent image is formed when irradiated with light and the latent image is rendered visible when heated, which includes a latent image forming light source for irradiating the recording material with incoherent light to form a latent image. The image forming apparatus gives no interference band.

Abstract: A high-k dielectric film is provided which remains amorphous at relatively high annealing temperatures. The high-k dielectric film is a metal oxide of either Zr or Hf, doped with a trivalent metal, such as Al. Because the film resists the formation of a crystalline structure, interfaces to adjacent films have fewer irregularities. When used as a gate dielectric, the film can be made thin to support smaller transistor geometries, while the surface of the channel region can be made smooth to support high electron mobility. Also provided are CVD, sputtering, and evaporation deposition methods for the above-mentioned, trivalent metal doped high dielectric films.