Abstract: A remanent, electrically programmable and erasable, memory device comprises of a MOS type transistor whose gate insulator contains charged mobile species is disclosed. The gate insulator is comprised transversely of a sandwich comprising at least five areas. Two intermediate areas have first band-gap values, and two endmost and a central areas have band gap values greater than the first values.

Abstract: A bipolar transistor and a method of fabricating the same are provided which are adapted to reduce chip size and production costs. To produce the transistor, a second conductive type well region is formed in a first conductive type semiconductor substrate and isolation trenches are formed at both sides of the well region. A high density second conductive type buried layer is formed in the semiconductor substrate which is formed at the bottom of the isolation trench. The buried layer is formed in two regions surrounding respective bottoms of two adjacent isolation trenches. The two regions are electrically connected with each other and in direct contact with the well region. An extrinsic base region and a device isolation region are formed sequentially onto the semiconductor substrate using a nitration layer pattern as a mask, wherein the nitration layer pattern is formed on the surface of semiconductor substrate.

Abstract: A MOS transistor for high-speed operation includes a gate insulator formed over a semiconductor substrate and a gate formed over the gate insulator. An insulating layer is formed on both sides of the gate insulator at the edge of the gate and thicker than the gate insulator. The device is also formed with LDD regions which form an LDD structure in the semiconductor substrate at least partially under the gate. The LDD structure defines a channel region under the gate insulator between the LDD regions. In one embodiment, the insulating layer formed on both sides of the gate extends toward the channel region but not beyond the LDD regions. In another embodiment, the insulating layer does extend beyond the LDD region but for a distance of less than 10 nm.

Abstract: An integrated circuit utilizing copper wiring has copper bond pads which are covered with a passivation layer to prevent unwanted reactions of the copper with metals which are bonded to it. The passivation layer can be an intermetallic of copper and titanium or a stacked layer of CuTix/TiN. Various nitrides can also be used, such as tungsten nitride, tantalum nitride, titanium silicon nitride, tungsten silicon nitride, and tantalum silicon nitride.

Abstract: A contact in a semiconductor memory device is formed on an active region of a cell array region, rather than on a sloped area between the cell array region and a core region. Preferably, an insulating layer on the active region is etched to form a hole therein and the contact formed through the hole. Preferably, the etching is performed using an etch solution having a high etch selectivity between the insulating layer and a top layer of the active region. Thus, the contact is evenly formed and the area of the cell array region is reduced, thereby enabling cells to be packed on a chip with high density.

Abstract: A circuit board with protrusions at desired locations on a wiring pattern that on the surface of the board. The protrusions are made of the same conductive material used in the wiring pattern, and formed unitarily and simultaneously with the wiring pattern. Conductive material is filled into grooves having different depths and formed on a film. The filled conductive material is transferred onto the board, and then fired. Thus the circuit board is manufactured. Semiconductor devices and general-purpose components are mounted on the circuit board, whereby a semiconductor device can be manufactured with high reliability and at an inexpensive cost.

Abstract: A method for forming contact plugs and simultaneously planarizing a substrate surface in an integrated circuit. Initially, a conductive structure is formed on a semiconductor substrate having a plurality of diffusion regions therein. A first insulating layer is formed over the semiconductor substrate including the conductive structure. The first insulating layer is etched using a contact hole forming mask to form a contact hole. A conductive layer is formed on the first insulating layer filling up the contact hole with the conductive layer. The conductive layer is etched until an upper surface of the first insulating layer is exposed. A second insulating layer is formed over the first insulating layer. A contact plug free of voids is formed and simultaneously a substrate surface is planarized by planarization-etching the second and first insulating layers.

Abstract: A semiconductor device includes a pair of second semiconductor regions (5) selectively formed in predetermined spaced apart relation in a first semiconductor region (3), and a silicide film (8) formed in an upper main surface of the first semiconductor region (3) between the pair of second semiconductor regions (5). The silicide film (8) is formed to establish an electric connection between side surfaces of the second semiconductor regions (5) at their respective edges opposed to each other. A source electrode (11) is formed on an upper surface of the silicide film (8). The semiconductor device has an increased safe operating area without the increase in manufacturing costs. A method of manufacturing the semiconductor device is also provided.

Abstract: A print system comprising an acquisition device for acquiring identifying information, a memory in which the identifying information acquired by the acquisition device and information about image processing performed to produce a print reproducing image in each of a plurality of frames recorded on film are stored in corresponding relationship with one other, and a condition setting device which sets image processing conditions based on a recorded image when producing an original print, and which retrieves, from the memory, information about image processing which corresponds to the identifying information when producing a re-print of the recorded image, setting image processing conditions for the re-print which are identical to those used for the original print.

Abstract: The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the robustness of electrostatic discharge (ESD) protection devices by reducing the temperature gradient caused by ESD pulses and reducing the likelihood of thermal runaway caused by large ESD pulses. The preferred embodiment forms implants under the trench isolation structures in the ESD devices. The implants reduce the current-caused heating that can lead to thermal runaway, and thus improve the robustness of the ESD protection device. In the preferred embodiment, the implants are formed using hybrid resist. The hybrid resist provides a method to form that implants that does not require additional masking steps or other excessive processing. Additionally, the hybrid resist provides implants that are self aligned with the well regions.

Abstract: A power MOS device that has increased channel width comprises a semiconductor substrate and a doped upper layer of a first conduction type disposed on the substrate. The upper layer comprises a plurality of doped well regions of a second, opposite conduction type and a plurality of heavily doped source regions of the first conduction type at an etched upper surface of the upper layer that comprises parallel corrugations disposed transversely to the source regions. A gate that separates one source region from another comprises an insulating layer and a conductive material. The corrugations provide an increase in width of a channel underlying the gate and the well and source regions.

Abstract: In a semiconductor device with a high breakdown voltage, insulating layers are buried at regions in n− silicon substrate located between gate trenches which are arranged with a predetermined pitch. This structure increases a carrier density at a portion near an emitter, and improves characteristic of an IGBT of a gate trench type having a high breakdown voltage.

Abstract: A reverse self-aligned field effect transistor and a method of fabricating the same are provided. The reverse self-aligned transistor includes a source formed on an active region of a semiconductor substrate and a drain formed on the active region of the semiconductor substrate, the drain being positioned a predetermined distance from the source. A silicide film is formed on the source and the drain. Insulative film spacers are formed on sidewalls of a trench, the trench being formed by etchin the semiconductor substrate between the source and the drain. A gate insulative film is formed on a lower portion of the trench and a metal gate is formed on the gate insulative film between the insulative film spacers. The metal gate is electrically isolated from the source and the drain by the insulative film spacers.

Abstract: A test device and method for determining parameters of a plurality of vias formed into a dielectric material making contact to a buried conductive layer. The present invention is comprised of a sample structure disposed within the material through which a plurality of vias are to be formed. The sample structure is adapted to enhance secondary electron yield from the via bottom during a scanning electron microscope examination of the vias. Additionally, the plurality of vias to be formed are disposed intentionally offset with respect to the sample structure. As a result, the enhanced secondary electron yield from the sample structure characterizes the degree of misalignment present in the via formation process. In so doing, the present invention simultaneously quantifies the critical dimension of the vias, the alignment/registration of the via formation process, and determines whether or not the vias are etched to a minimum desired depth.

Abstract: A probe is provided with a thermocouple made of a joint between a first metal material and a second metal material. The first metal material is formed on the surface of a flexible plate facing a substrate, continuously from the thermocouple portion. The surface of the flexible plate facing the substrate is formed with a first wiring conductive film, which is electrically connected to the first metal material and extends over the proximal end side area of the flexible plate.

Abstract: A semiconductor package, and a method for fabricating the package are provided. The package includes a semiconductor die, a lead frame, and a metal foil die mounting plate adapted to mount the die to the lead frame. In addition, the die mounting plate provides a thermally conductive path from the die to terminal leads of the package. Further, the die mounting plate can be configured to perform electrical functions, such as providing ground/power planes for the package, and adjusting an impedance of signal paths through the package. In a first embodiment the package can be fabricated using a tape under frame lead frame. In a second embodiment the package can be fabricated using a lead under chip lead frame.

Abstract: A semiconductor device includes the first through third semiconductor devices which are stacked on a substrate and the first through third wires for connecting the semiconductor elements and the substrate. The first wires serve to connect electrodes of the first semiconductor element positioned uppermost and electrodes of the second semiconductor element. The second wires serve to connect the electrodes of the second semiconductor element and electrodes of the third semiconductor element. The third wires serve to connect the electrodes of the third semiconductor element and bonding pads of the substrate. Between the first wires and the electrodes of the second semiconductor element and between the second wires and the electrodes of the third semiconductor element, stud bumps are provided so as to form space therebetween, thereby avoiding short-circuits therebetween.

Abstract: Leakage current may be reduced in trench isolated semiconductor devices by providing a buffer between the trench isolation and an active area. For example, with a trench isolated photodiode, a buffer of opposite conductivity type may be provided between the trench and the diffusion that forms the p-n junction of the photodiode.

Abstract: A MOSFET has a buried shield plate under the gate and over the drain with the gate being formed on the periphery of the buried shield plate as a self-aligned structure with minimal or no overlap of the gate over the shield plate. Methods of fabricating the MOSFET are disclosed.

Abstract: An IC module has one or more integrated circuits and a package surrounding them. The IC module is distinguished by one or more additional electronic components being accommodated inside the package, in the immediate vicinity of the integrated circuit.