Patents Examined by Eddie Lee
  • Patent number: 7215029
    Abstract: In order to solve the aforementioned problems, the present-invention provides a semiconductor device having a multilayer interconnection structure, wherein an upper interconnection comprises a first metal layer composed of an aluminum alloy, which is formed over a lower interconnection, and a second metal layer formed over the first metal layer and composed of an aluminum alloy formed as a film at a temperature higher than that for the first metal layer. Another invention provides a semiconductor device having a multilayer interconnection structure, wherein a metal region composed of a metal different from an aluminum alloy is formed in a portion spaced by a predetermined distance in an extending direction of an upper interconnection from an end of a via hole defined in the upper interconnection composed of the aluminum alloy, which is electrically connected to a lower interconnection through the via hole.
    Type: Grant
    Filed: January 5, 1999
    Date of Patent: May 8, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Eiichi Umemura
  • Patent number: 7202569
    Abstract: A semiconductor device comprises a semiconductor element which is flip-chip bonded to a circuit substrate. The semiconductor element and the circuit substrate are flip-chip bonded using a sealing resin having flux function. The semiconductor element includes a solder bump formed on a first electrode pad through a first low melting point solder layer. The circuit substrate includes a second electrode pad corresponding to the first electrode pad, and a second low melting point solder layer is formed on the second electrode pad. The solder bump is bonded to the first and second electrode pads through the first and second low melting point solder layers.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: April 10, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akira Tomono
  • Patent number: 7183166
    Abstract: A semiconductor device having a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure is formed by providing a first silicon oxide layer and a silicon nitride layer over a substrate having a memory region and a logic device region; patterning the first silicon oxide layer and the silicon nitride layer to define bottom oxide and silicon nitride portions of partially completed ONO stacks and to expose the substrate in the logic device regions; performing a rapid thermal annealing process in the presence of a radical oxidizing agent to form concurrently a second silicon oxide layer on the exposed surface of the silicon nitride layer and a gate oxide layer over the substrate; and depositing a conductive layer over the completed ONO stacks and the gate oxide. The invention is employed in manufacture of, for example, memory devices having and peripheral logic devices and memory cells including ONO structures.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: February 27, 2007
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih-Hao Wang, Hsin-Huei Chen, Chong-Jen Huang, Kuang-Wen Liu, Jia-Rong Chiou, Chong-Mu Chen
  • Patent number: 7183602
    Abstract: Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.
    Type: Grant
    Filed: January 11, 2005
    Date of Patent: February 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: K. R. Udayakumar, Theodore S. Moise, Scott R. Summerfelt
  • Patent number: 7164154
    Abstract: A silicon carbide semiconductor device includes: a semiconductor substrate including first and second gate layers, a channel layer, a source layer, and a trench; a gate wiring having a first portion and a plurality of second portions; and a source wiring having a third portion and a plurality of fourth portions. The trench extends in a predetermined extending direction. The first portion connects to the first gate layer in the trench, and extends to the extending direction. The second portions protrude perpendicularly to be a comb shape. The third portion extends to the extending direction. The fourth portions protrude perpendicularly to be a comb shape, and electrically connect to the source layer. Each of the second portions connects to the second gate layer through a contact hole.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: January 16, 2007
    Assignee: Denso Corporation
    Inventors: Rajesh Kumar, Yuichi Takeuchi, Mitsuhiro Kataoka, Suhail Rashid Jeremy, Andrei Mihaila, Florin Udrea
  • Patent number: 7157796
    Abstract: A SiP type semiconductor device and a method of producing the same is provided wherein curvature of a wafer is suppressed in the production steps, workability does not decline, and high throughput can be attained. An insulation layer is formed by stacking a plurality of resin layers on a semiconductor substrate, wiring layers are formed by being buried in the insulation layer so as to be connected to an electronic circuit, an insulating buffer layer for buffering a stress generated at the time of being mounted on a board is formed on the insulation layer, a conductive post is formed through the buffer layer and connected to the wiring layer, and a projecting electrode is formed projecting from a surface of the buffer layer and connected to the conductive post.
    Type: Grant
    Filed: November 17, 2004
    Date of Patent: January 2, 2007
    Assignee: Sony Corporation
    Inventor: Osamu Yamagata
  • Patent number: 7151307
    Abstract: A semiconductor device having at least one layer of a group III–V semiconductor material epitaxially deposited on a group III–V nucleation layer adjacent to a germanium substrate. By introducing electrical contacts on one or more layers of the semiconductor device, various optoelectronic and microelectronic circuits may be formed on the semiconductor device having similar quality to conventional group III–V substrates at a substantial cost savings. Alternatively, an active germanium device layer having electrical contacts may be introduced to a portion of the germanium substrate to form an optoelectronic integrated circuit or a dual optoelectronic and microelectronic device on a germanium substrate depending on whether the electrical contacts are coupled with electrical contacts on the germanium substrate and epitaxial layers, thereby increase the functionality of the semiconductor devices.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: December 19, 2006
    Assignee: The Boeing Company
    Inventors: Karim S. Boutros, Nasser H. Karam, Dimitri D. Krut, Moran Haddad
  • Patent number: 7138714
    Abstract: The present invention provides an interconnect structure that includes a diffusion barrier which is positioned within the structure in a fashion that increases the reliability and lifetime of the interconnect structure.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: November 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Du B. Nguyen, Birendra N. Agarwala, Conrad A Barile, Jawahar P. Nayak, Hazara S. Rathore
  • Patent number: 7138326
    Abstract: A shadow mask for depositing solder bumps includes additional dummy holes located adjacent holes corresponding to most of the perimeter chips of the wafer. The additional dummy provide more uniform plasma etching of contacts of the wafer, improve etching of contacts of perimeter chips, and lower contact resistance of contacts of perimeter chips. The extra holes also provide solder bumps outside the perimeter chips that can be used to support a second shadow mask for deposition of an additional material, such as tin, on the reflowed solder bumps for mounting the chips on a plastic substrate at low temperature. An improved mask to wafer alignment aid is formed from standard solder bumps. The improved alignment aid avoids damage to test probes and provides improved course alignment.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: November 21, 2006
    Assignee: International Business Machines Corp.
    Inventors: Harry D. Cox, David P. Daniel, Leonard J. Gardecki, Albert J. Gregoritsch, III, Ruth A. Machell Julianelle, Charles H. Keeler, Doris P. Pulaski, Mary A. Schaffer, David L. Smith, David J. Specht, Adolf E. Wirsing
  • Patent number: 7129176
    Abstract: An optical device includes a semiconductor substrate and an optical part having a plurality of columnar members disposed on the substrate. Each columnar member is disposed in a standing manner and adhered each other so that the optical part is provided. The optical part is integrated with the substrate. This optical part has high design freedom.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: October 31, 2006
    Assignee: Denso Corporation
    Inventors: Junji Oohara, Kazuhiko Kano, Yoshitaka Noda, Yukihiro Takeuchi, Toshiyuki Morishita
  • Patent number: 7126159
    Abstract: A light emitting device includes a first patterned electrode 12 and a second patterned electrode 13 both of which are formed on a wiring board 11, an LED chip 19 mounted on the second patterned electrode 13, a metal wire 20 electrically connecting the LED chip 19 and the first patterned electrode 12 to each other, and a lens member 21 made of a transparent synthetic resin for packaging the LED chip 19 and the metal wire 20. The first patterned electrode 12 is circular and formed with a cutout 14 at the center thereof. The second patterned electrode 13 is arranged in the cutout 14. With this arrangement, the lens member 21 can be formed into a predetermined configuration, while the reflection of light by the patterned electrodes can be ensured.
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: October 24, 2006
    Assignee: Rohm Co., Ltd.
    Inventors: Junichi Itai, Takayuki Ishihara, Takeshi Kitamura
  • Patent number: 7119398
    Abstract: A power-up and power-down circuit for an integrated circuit includes a voltage regulator set for a first voltage. A first I/O pad is coupled internally to an input to the voltage regulator and to first internal circuits. The second voltage is externally coupled to the first I/O pad. A second I/O pad is coupled internally to an output of the voltage regulator configured to drive the base of an external transistor. A third I/O pad of the integrated circuit is coupled internally to a reference-voltage input of the voltage regulator. A fourth I/O pad is coupled to a feedback input of the voltage regulator. A fifth I/O pad of the integrated circuit is coupled internally to logic circuitry that controls power-up and power down of the integrated circuit from internal signals including internal signals from a real-time clock circuit disposed on the integrated circuit.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: October 10, 2006
    Assignee: Actel Corporation
    Inventor: Gregory Bakker
  • Patent number: 7112820
    Abstract: A capacitor structure includes a first conductive layer, a first insulating layer disposed on a substrate in sequence, a second conductive layer disposed on portions of the first insulating layer, a second insulating layer disposed on the second conductive layer and the first insulating layer, a third conductive layer disposed on portions of the second insulating layer, a third insulating layer disposed on the third conductive layer and the second insulating layer, and a fourth conductive layer disposed on the third insulating layer. The third conductive layer and the fourth conductive layer are electrically connected to the first conductive layer and the second conductive layer through at least one first contact hole adjacent to the second conductive layer and at least one second contact hole, respectively.
    Type: Grant
    Filed: September 1, 2003
    Date of Patent: September 26, 2006
    Assignee: AU Optronics Corp.
    Inventors: Chih-Chin Chang, Kuang-Chao Yeh
  • Patent number: 7101763
    Abstract: The present invention provides a SiGe-based bulk integration scheme for generating FinFET devices on a bulk Si substrate in which a simple etch, mask, ion implant set of sequences have been added to accomplish good junction isolation while maintaining the low capacitance benefits of FinFETs. The method of the present invention includes providing a structure including a bottom Si layer and a patterned stack comprising a SiGe layer and a top Si layer on the bottom Si layer; forming a well region and isolation regions via implantation within the bottom Si layer; forming an undercut region beneath the top Si layer by etching back the SiGe layer; and filling the undercut with a dielectric to provide device isolation, wherein the dielectric has an outer vertical edge that is aligned to an outer vertical edge of the top Si layer.
    Type: Grant
    Filed: May 17, 2005
    Date of Patent: September 5, 2006
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 7102213
    Abstract: A leadframe-based housing for a surface-mountable component, particularly a radiation-emitting component. The leadframe-based housing comprises electrical connector strips and at least one chip mounting area. One of the connector strips includes an injection aperture that enables a leadframe-based housing to be produced with a very small thickness in an injection molding process. A method for producing such housings is further specified.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: September 5, 2006
    Assignee: Osram Opto Semiconductors GmbH
    Inventor: Jörg Erich Sorg
  • Patent number: 7098113
    Abstract: A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accordingly, in a first approach the standard process flow will be followed until reaching the point where contact openings and metal are to be processed. In this approach slots are etched that are preferably 5 to 6 um deep and 5 to 6 um wide. These slots are then oxidized and will be subsequently metalized. When used for making metal contacts to the buried layer or for ground the oxide is removed from the bottom of the slots by an anisotropic etch. Subsequently when these slots receive metal they will provide contacts to the buried layer where this is desired and to the substrate when a ground is desired. In a second approach the above-identified process is completed up through the slot process without processing the lateral PNPs.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: August 29, 2006
    Assignee: Micrel, Inc.
    Inventors: John Durbin Husher, Ronald L. Schlupp
  • Patent number: 7098512
    Abstract: Layout patterns for the deep well region to facilitate routing the body-bias voltage in a semiconductor device are provided and described. The layout patterns include a diagonal sub-surface mesh structure, an axial sub-surface mesh structure, a diagonal sub-surface strip structure, and an axial sub-surface strip structure. A particular layout pattern is selected for an area of the semiconductor device according to several factors.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: August 29, 2006
    Assignee: Transmeta Corporation
    Inventors: Mike Pelham, James B. Burr
  • Patent number: 7098527
    Abstract: A configuration for a conventional lead frame for conserving limited leads and for allowing the location of bond pads anywhere on the periphery of the semiconductor device and for reducing the cost of tooling changes by permitting the use of current tooling. The present invention utilizes an extended lead finger that extends along the periphery of a semiconductor device to provide a power source or ground so that any number of bond pads may be used in any position without requiring additional leads or tooling changes.
    Type: Grant
    Filed: August 4, 2003
    Date of Patent: August 29, 2006
    Assignee: Micron Technology, Inc.
    Inventors: David J. Corisis, Jerry M. Brooks
  • Patent number: 7095079
    Abstract: An injection enhanced gate transistor includes a drift layer, a collector layer and a base layer divided into main cell regions and dummy cell regions by a plurality of trenches formed to extend from the top surface of the base layer into the drift layer. The main cell has a first emitter layer selectively formed in the surface layer of the base layer, gate electrodes formed in the trenches, and an emitter electrode located over the base layer. The dummy cell has a second emitter layer selectively formed so as to be scattered in the surface layer of the base layer and have a surface area smaller than that of the first emitter layer to prevent waveform vibration associate with negative gate capacitance.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: August 22, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takahiro Okuno, Masahiro Tanaka
  • Patent number: 7094660
    Abstract: A semiconductor device has a stabilizing member that encloses an upper portion of a storage electrode to improve structural stability. A dielectric layer and a plate electrode are successively formed on the storage electrode including a stabilizing member. Since the stabilizing member includes a protruding portion to support the storage electrode and an adjacent storage electrode, all of the storage electrodes in a unit cell of a semiconductor device are structured to prevent a collapse. Also, the semdevice can have a very high height without collapse when the capacitors have extremely high aspect ratios. Therefore, the capacitors may have greatly enhanced capacitance in comparison with a conventional capacitor.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: August 22, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Je-Min Park