Abstract: Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described.

Abstract: A light-emitting diode includes: a semiconductor substrate; and a layered structure, made of an AlGaInP type compound semiconductor material and provided on the semiconductor substrate. The layered structure includes: a light-emitting structure composed of a pair of cladding layers and an active layer for emitting light provided between the pair of cladding layers; and a current diffusion layer which is lattice-mismatched with the light-emitting structure. A lattice mismatch ?a/a of the current diffusion layer with respect to the light-emitting structure defined by the following expression is ?1% or smaller: ?a/a=(ad?ae)/ae where ad is a lattice constant of the current diffusion layer, and ae is a lattice constant of the light-emitting structure.

Abstract: A light source including a specific LED and phosphor combination capable of emitting white light for direct illumination. In one embodiment, the light source includes an LED chip emitting in the 460-470 nm range radiationally coupled to a phosphor comprising Ca8Mg(SiO4)4Cl2:Eu2+,Mn2+. In a second embodiment, the light source includes an LED chip emitting at about 430 nm and a phosphor comprising a blend of Sr4Al14O25:Eu2+ (SAE) and a second phosphor having the formula(Tb1-x-yAxREy)3DzO12, where A is a member selected from the group consisting of Y, La, Gd, and Sm; RE is a member selected from the group consisting of Ce, Pr, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb, and Lu; D is a member selected from the group consisting of Al, Ga, and In; x is in the range from 0 to about 0.5, y is in the range from about 0 to about 0.2, and z is in the range from about 4 to about 5. Both embodiments produce light having the coordinates x=0.240-0.260 and y=0.340-0.360 on the CIE chromaticity diagram.

Abstract: A semiconductor device has a die (10) overlying and electrically connected to a support structure (11), such as a substrate or a lead frame, via a plurality of interconnects. Aggressor interconnects (32, 38) are noise sources to victim interconnects (29, 59) carrying sensitive signals. An arrangement of shield interconnects (51-58) surround the victim interconnect (29, 59) in a cage-like structure to significantly block noise from the aggressor interconnect. In one form the shield interconnects are ground or power supply and the victim interconnect may be, for example, a clock signal or an RF signal. The number of shield interconnects and the number of protected victim interconnects varies depending upon design requirements. Either wire bonding or other interconnect technology (e.g. bump) is applicable.

Abstract: A power semiconductor device including a non-doped GaN channel layer, an n-type Al0.2Ga0.8N barrier layer formed on the channel layer, a p-type Al0.1Ga0.9N semiconductor layer selectively formed on the barrier layer, a drain electrode positioned at one of both sides of the semiconductor layer and formed on the barrier layer, an insulating film formed on the barrier layer adjacent to the semiconductor layer between at least semiconductor layer and drain electrode, and a field plate electrode formed on the insulating film.

Abstract: A high frequency switch device includes an epitaxy substrate that is formed by sequentially stacking an AlGaAs/GaAs superlattic buffer layer, a first Si planar doping layer, an undoped first AlGaAs spacer, an undoped InGaAs layer, an undoped second AlGaAs spacer, a second Si planar doping layer having a doping density greater than that of the first Si planar doping layer, and an undoped GaAs/AlGaAs capping layer on a GaAs semi-insulated substrate. The undoped GaAs/AlGaAs capping layer is formed with a source electrode and a drain electrode that form an ohmic contact with the undoped GaAs/AlGaAs capping layer thereon, and a gate electrode formed between the source electrode and the drain electrode, thereby forming a Schottky contact with the undoped GaAs/AlGaAs capping layer.

Abstract: A wire bonding technique for manufacturing semiconductor devices that results in a bonded wire having a small loop height. The wire bonding technique involves a capillary tool that ball bonds a wire to a first contact point, then moves upwards, and then towards a second contact point to which the wire will be attached. The capillary tool only moves towards the second contact point in the lateral direction. The height of the wire loop of the bonded wires can be controlled to have desired wire loop heights. The bonding technique can be used in semiconductor devices with stacked dice and in devices where a die and a contact lead are approximately at the same height.

Abstract: The present invention relates to a process for vapor depositing a low dielectric insulating film, a thin film transistor using the same, and a preparation method thereof, and more particularly to a process for vapor deposition of lowdielectric insulating film that can significantly improve a vapor deposition speed while maintaining properties of the low dielectric insulating film, thereby solving parasitic capacitance problems to realize a high aperture ratio structure, and can reduce a process time by using silane gas when vapor depositing an insulating film by a CVD or PECVD method to form a protection film for a semiconductor device. The present invention also relates to a thin film transistor using the process and preparation method thereof.

Abstract: A leadless leadframe semiconductor package having a plurality of contacts, which have contact surfaces on the bottom surface of the package. At least some of the contacts have integrally formed stems that extend outward to the peripheral surface of the package. These stems have heights and widths less than the heights and widths of their corresponding contacts. A molded cap encapsulates at least a portion of the die, the stems and the contacts. Another aspect of the invention pertains to a leadless leadframe panel assembly having a conductive substrate panel that has at least one array of device areas, each array of device areas having a plurality of tie bars and a plurality of contacts. The contacts also have integrally formed stems that extend towards and connect to one of the tie bars. The stems have widths and heights that are less than the widths and heights of their corresponding contacts.

Abstract: A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating-body effect and improves isolation performance and breakdown voltage, and a method of manufacturing the semiconductor device can be obtained.

Abstract: A bottom-gate thin-film transistor includes a gate electrode, a gate insulating film, an active layer, and a protective insulating film deposited in that order on a substrate. The protective insulating film has a thickness of 100 nm or less, and the protective insulating film is formed on any one of the active layer, and LDD region, and a source-drain region. A method for making a bottom-gate thin-film transistor, a liquid crystal display device including a TFT substrate using the bottom-gate thin-film transistor and a method for fabricating the same, and an organic EL device including the bottom-gate thin-film transistor and a method for fabricating the same are also disclosed.

Abstract: In a NPN transistor electrostatic discharge (ESD) protection structure, certain parameters, including maximum lattice temperature, are improved by introducing certain process changes to provide for SCR-like characteristics during ESD events. A p+region is formed adjacent the collector to define a SCR-like emitter and with a common contact with the collector of the BJT. The p+ region is spaced from the n-emitter of the transistor by a n-epitaxial region, and the collector is preferably spaced further from the n-emitter than is the case in a regular BJT.

Abstract: A cascaded die mounting device and method using spring contacts for die attachment, with or without metallic bonds between the contacts and the dies, is disclosed. One embodiment is for the direct refrigerant cooling of an inverter/converter carrying higher power levels than most of the low power circuits previously taught, and does not require using a heat sink.

Abstract: A semiconductor mounting arrangement inclusive of a heat sink member enabling desirable resistance to physical impact damage to the semiconductor device, the heat sink and the printed circuit board supporting the semiconductor device and the heat sink. The heat sink is fabricated of thermally and electrically conductive metal such as copper and captured by metallic interconnection such as soldering to conductors of the printed circuit board. Efficient thermal and electrical conductivity between semiconductor device and heat sink are achieved also by metallic interconnection such as soldering intermediate the semiconductor device and the heat sink. Desirable semiconductor device performance under extreme electrical and physical force transient loading conditions are disclosed.

Abstract: An exemplary system and method for providing a vertically integrated photosensing element suitably adapted for use in CMOS imaging applications is disclosed as comprising inter alia: a processed CMOS layer (420); and a photosensing element (380) fabricated in a vertically integrated optically active layer (320, 350), where the optically active layer (320, 350) is bonded to the CMOS layer (420) and the optically active layer (320, 350) is positioned near a metalization surface (405) of the CMOS layer (420). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize photosensing performance or other material characteristics.

Abstract: A first insulator (710) having an opening within a central region (551) is formed on a main surface (61S) of an epitaxial layer (610). Then, p-type impurities are ion implanted through the opening of the first insulator (710) and then heat treatment is carried out, thereby to form a p base layer (621) in the main surface (61S). An insulating film is formed to fill in the opening and then etched back, thereby to form a second insulator (720) on a side surface (71W) of the first insulator (710). Under conditions where the second insulator (720) is present, n-type impurities are ion implanted through the opening and then heat treatment is carried out, thereby to form an n+ source layer (630) in the main surface (61S) of the p base layer (621).

Abstract: A method of fabricating an X-ray detecting device that is capable of preventing breakage of a transparent electrode. In the method, patterning of first and second insulating films occurs at different etching rates, with an etching ratio of the second insulating material to the first insulating material being greater than 1. Accordingly, undercut of the first and second insulating materials can be prevented. This stabilizes the step coverage of a subsequently formed transparent electrode.

Abstract: A semiconductor device, including a dummy diffused layer in the upper part of a substrate, has its noise immunity improved. The dummy diffused layer is formed between analog and digital blocks to eliminate dishing, which usually occurs during a CMP process for defining STI regions. The surface of the dummy diffused layer is covered with an anti-silicidation film at least partially and a dummy gate electrode so as not to be silicided. The dummy gate electrode can be formed along with a normal gate electrode for a transistor.

Abstract: A semiconductor device and a manufacturing method therefor reduce the occurrence of variation in threshold voltage of a MOS transistor formed by a dual oxide process, thereby to improve manufacturing yield. On the main surface of a semiconductor substrate (1), gate oxide films (GX1, GX2) of different thickness are located in active regions (3A, 3B), respectively, and gate electrodes (GT1, GT2) are located on top of the gate oxide films (GX1, GX2), respectively. An isolation insulating film (2) which defines the active region (3A) in a thick-film portion (AR) has an excessively removed edge portion on the side of a MOS transistor (100) and thereby a recessed portion (DP) is formed in the edge portion of the active region (3A). On the other hand, an edge portion of the isolation insulating film (2) in a thin-film portion (BR) on the side of a MOS transistor (200) is not excessively removed.

Abstract: A method of manufacturing a semiconductor device involves mounting a semiconductor chip, formed on top with a main electrode and a subelectrode smaller in area than the main electrode, on a die pad of an external lead frame through a first bonding material, mounting an inner lead frame in which plural inner leads for connecting the main electrode and the subelectrode on the chip to corresponding connecting pads of the external lead frame are joined together by a tie bar on the chip and the external lead frame through a second bonding material, heating the first and second bonding materials simultaneously for electrically connecting and fixing the chip to the die pad and the inner leads to the electrodes on the chip and the connecting pads of the external lead frame, and cutting the tie bar to separate the inner lead frame into the plural inner leads.