Patents Examined by Eddie Lee
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Patent number: 6919230Abstract: A preformed adhesive layer for joining components within integrated circuit packaging includes venting slots for controlling the size and location of voids within an assembled integrated circuit package. Air randomly entrapped between the surfaces of the adhesive layer and adjoining components during assembly will generally release into the venting slots during subsequent assembly and/or mounting steps performed at elevated temperatures, rather than creating internal pressures causing separation of package components or releasing into the encapsulant. Die delamination and encapsulant void problems occurring during reflow or other assembly and mounting processes as a result of entrapped air are avoided.Type: GrantFiled: January 12, 2004Date of Patent: July 19, 2005Assignee: STMicroelectronics, Inc.Inventor: Anthony M. Chiu
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Patent number: 6917077Abstract: A semiconductor arrangement including: a substrate having a substrate layer (13) with an upper and lower surface, the substrate layer (13) being of a first conductivity type; a first buried layer (12) in the substrate, extending along said lower surface below a first portion of said upper surface of said substrate layer (13), and a second buried layer (12) in the substrate, extending along said lower surface below a second portion of said upper surface of said substrate layer (13); a first diffusion (26) in said first portion of said substrate layer (13), being of a second conductivity type opposite to said first conductivity type and having a first distance to said first buried layer (12) for defining a first breakdown voltage between said first diffusion (26) and said first buried layer (12); a second diffusion (45) in said second portion of said substrate layer (13), being of said second conductivity type and having a second distance to said second buried layer (12) for defining a second breakdown voltaType: GrantFiled: October 5, 2001Date of Patent: July 12, 2005Assignee: Koninklijke Philips Electronics N.V.Inventors: Petrus Hubertus Cornelis Magnee, Freerk Van Rijs, Hendrik Gezienus Albert Huizing
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Patent number: 6917103Abstract: A semiconductor device includes a semiconductor chip, a first heat sink, a second heat sink, and a mold resin. The first heat sink is electrically and thermally connected to a surface of the semiconductor chip for functioning as an electrode for the semiconductor chip and releasing the heat generated by the semiconductor chip. The second heat sink is electrically and thermally connected to another surface of the semiconductor chip for functioning as another electrode for the semiconductor chip and releasing the heat. The semiconductor chip and the first and second heat sinks are covered with the mold resin such that the heat sinks are exposed on a substantially flat surface of the mold resin.Type: GrantFiled: December 23, 2002Date of Patent: July 12, 2005Assignee: Denso CorporationInventors: Naohiko Hirano, Takanori Teshima, Yoshimi Nakase, Shoji Miura
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Patent number: 6917112Abstract: A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g.. ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the metal oxide regions are formed by diffusion of oxygen through grain boundaries of the metal layer, e.g., platinum, to oxidize a metal layer thereon, e.g, ruthenium layer. The structure is particularly advantageous for use in capacitor structures and memory devices, such as dynamic random access memory (DRAM) devices.Type: GrantFiled: August 26, 2002Date of Patent: July 12, 2005Assignee: Micron Technology, Inc.Inventors: Cem Basceri, Gurtej Sandhu
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Patent number: 6914301Abstract: CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2<x<0.Type: GrantFiled: October 14, 2003Date of Patent: July 5, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Geum-jong Bae, Tae-hee Choe, Sang-su Kim, Hwa-sung Rhee, Nae-in Lee, Kyung-wook Lee
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Patent number: 6914327Abstract: A semiconductor device includes a substrate which has a main surface, a back surface, and a through hole. The semiconductor device also includes an insulating film formed on an inner wall of the through hole, a conductive member provided on the insulating film within the through hole, an external terminal provided above the main surface, and a wiring portion connected to the external terminal. The semiconductor device also includes an encapsulating layer which covers the main surface and the wiring portion except for a portion to which the external terminal is connected. A side surface of the encapsulating layer is formed inside a side surface of the substrate.Type: GrantFiled: May 20, 2004Date of Patent: July 5, 2005Assignee: Oki Electric Industry Co., Ltd.Inventor: Yoshinori Shizuno
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Patent number: 6914321Abstract: It is an object to provide a semiconductor device having an improved heat dissipation characteristic. A power element is mounted on and jointed and to a metal block through a jointing material. An insulating substrate includes a ceramic substrate and metal layers formed on both surfaces of the ceramic substrate and having thicknesses equal to each other. The metal block and the insulating substrate are provided per insulation unit of the power element. The metal layer of the insulating substrate is joined to a surface of the metal block through a jointing material opposite to a surface thereof for forming the power element. An electrode terminal is attached to a surface of the metal block having a power element joined thereto through ultrasonic junction and the like. Electrode terminals are connected to electrodes of the power element through aluminum wires.Type: GrantFiled: July 2, 2001Date of Patent: July 5, 2005Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Toshiaki Shinohara
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Patent number: 6911721Abstract: A semiconductor device includes a base substrate provided with a base wiring. A first substrate includes a first wiring to be electrically connected to the base wiring and is provided above the base substrate. A first semiconductor element includes a first electrode to be electrically connected to the first wiring and is provided between the base substrate and the first substrate. A second substrate includes a second wiring to be electrically connected to the base wiring and is provided above the first substrate. A second semiconductor element includes a second electrode to be electrically connected to the second wiring and is provided between the first substrate and the second substrate and above the first semiconductor element. The first substrate has a first region where the first semiconductor element is provided below, a second region where a portion of the first wiring that connects to the base wiring is located, and a first bent section between the first region and the second region.Type: GrantFiled: August 21, 2003Date of Patent: June 28, 2005Assignee: Seiko Epson CorporationInventor: Akiyoshi Aoyagi
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Patent number: 6906357Abstract: An apparatus including an electrostatic discharge (ESD) protection structure with a diac in which substancially similar ESD protection is provided for both positive and negative ESD voltages appearing at the circuit electrode sought to be protected.Type: GrantFiled: October 10, 2003Date of Patent: June 14, 2005Assignee: National Semiconductor CorporationInventors: Vladislav Vashchenko, Marcel ter Beek, Peter J. Hopper, Ann Concannon
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Patent number: 6906384Abstract: A semiconductor device includes first and second semiconductor layers and first and second MOS transistors. The first semiconductor layer is provided on and electrically connected to the semiconductor substrate. The second semiconductor layer is provided near the first semiconductor layer and formed above the semiconductor substrate via one of an insulating film and a cavity. The first and second MOS transistors are respectively provided on the first and second semiconductor layers, and each has a gate electrode arranged parallel to a boundary between the first and second semiconductor layers.Type: GrantFiled: March 14, 2002Date of Patent: June 14, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yamada, Tsutomu Sato, Shinichi Nitta, Hajime Nagano, Ichiro Mizushima, Hisato Oyamatsu, Yoshihiro Minami, Shinji Miyano, Osamu Fujii
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Patent number: 6903438Abstract: A decoupling device for decoupling a high-frequency noise wave in a digital circuit is formed as a line device including a portion of a semiconductor substrate, an insulator film formed thereon as a gate oxide film, and an interconnect line formed thereon as a gate electrode. The line capacitance between the interconnect line and the semiconductor substrate is 100 pF or above, whereby the decoupling device effectively decouples the electromagnetic noise wave generated by a switching device in a frequency range between 10 and 1000 GHz.Type: GrantFiled: April 8, 2003Date of Patent: June 7, 2005Assignee: NEC CorporationInventors: Takashi Nakano, Hirokazu Tohya
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Patent number: 6903465Abstract: A method for packaging a semiconductor device includes connecting a plurality of wire leads to a corresponding plurality of electrical connection pads on the semiconductor device, covering at least a portion of the semiconductor device and at least a portion of each of the wire leads with an encapsulating material, and removing a portion of the encapsulating material and a portion of each of the wire leads to form a packaged semiconductor device wherein each of the wire leads has an exposed portion only at an end. The invention also includes a packaged semiconductor device having an integrated circuit device with a plurality of electrical connection pads, a plurality of wire leads coupled to the plurality of electrical connection pads, and a covering of encapsulating material covering at least a portion of the integrated circuit device and covering each of the wire leads, wherein each of the wire leads has an exposed end.Type: GrantFiled: September 10, 2001Date of Patent: June 7, 2005Assignee: Micron Technology, Inc.Inventors: Warren Farnworth, Larry Kinsman, Walter Moden
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Patent number: 6900526Abstract: A semiconductor device package is comprised of a metal base for receiving a semiconductor device, a metal frame joined at its lower face to the metal base, a seal ring joined at its lower face to an upper face of the metal frame, and a metal lid joined to an upper face of the seal ring. The upper face of the seal ring is formed, at its at least two sides facing each other, into a concavely warped shape as viewed in vertical cross section, and the maximum warpage of the upper face of the seal ring is not more than 0.2% of the length of the side of the upper face.Type: GrantFiled: May 22, 2003Date of Patent: May 31, 2005Assignee: The Furukawa Electric Co., Ltd.Inventors: Takahiro Okada, Hideaki Murata
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Patent number: 6900085Abstract: One aspect of the present invention provides a process for forming IC devices with ESD protection transistors. According to one aspect of the invention, an ESD protection transistor is provided with a light doping and then, after forming spacers, a heavy doping. The heavy doping with spacers in place can lower the sheet resistance, enhance the bipolar effect for the transistor, reduce the transistor's capacitance, and reduce the junction breakdown voltage, all without causing short channel effects. The invention thereby provides ESD protection transistors that are compact, highly sensitive, and fast-switching. The spacers can be formed at the same time as spacers for other transistors, such as other transistors in a peripheral region of the device.Type: GrantFiled: June 26, 2001Date of Patent: May 31, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Mark T. Ramsbey, Michael Fliesler, Mark Randolph, Mimi Qian, Yu Sun
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Patent number: 6900466Abstract: A semiconductor component for generating a polychromatic electromagnetic radiation has a semiconductor chip with a first semiconductor layer and a second semiconductor layer, which is provided adjacent to the first semiconductor layer and has an electroluminescent region. The electroluminescent region emits electromagnetic radiation of a first wavelength. The first semiconductor layer includes a material which, when excited with the electromagnetic radiation of the first wavelength, re-emits radiation with a second wavelength which is longer than the first wavelength.Type: GrantFiled: July 25, 2001Date of Patent: May 31, 2005Assignee: Osram GmbHInventors: Detlef Hommel, Helmut Wenisch
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Patent number: 6900504Abstract: The integrated structure and process is effective to form, in a dielectrically insulated well, a MOS component including respective drain and source regions of a first conductivity type as well as a gate region. The integrated structure includes a cut-off layer of the second conductivity type effective to surround only the source region. The cut-off layer is self-aligned by the gate region.Type: GrantFiled: May 21, 2003Date of Patent: May 31, 2005Assignee: STMicroelectronics S.r.l.Inventor: Salvatore Leonardi
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Patent number: 6900517Abstract: A non-volatile memory, which comprises an insulating substrate (11) that has a first electrode (18) that extends through the substrate from the front surface to the rear surface thereof; a second electrode (13) that is formed on one side of the insulating substrate (11); and a recording layer (12) that is clamped between the first electrode (18) and the second electrode (13) and whose resistance value varies when an electric pulse is applied across the first electrode (18) and the second electrode (13); wherein the insulating substrate (11) has a layered structure composed of an organic dielectric thin film (112) and an inorganic dielectric layer (111) that is thinner than the organic dielectric thin film (112); with the recording layer (12) being formed on the side on which the inorganic dielectric layer is formed. Use of this non-volatile memory increases the possible number of data writing cycles while saving power.Type: GrantFiled: August 25, 2003Date of Patent: May 31, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hideyuki Tanaka, Kiyoshi Morimoto
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Patent number: 6900090Abstract: A device isolation structure in a semiconductor device and a method for fabricating the same are disclosed. A trench is formed in a semiconductor substrate to confine a plurality of active regions, an insulating material is deposited to fill the trench and the insulating material having a portion extending from the trench to above the semiconductor substrate, and a trench oxidation preventive film is formed on the insulating material. The semiconductor device preferably further includes a gate line extending in one direction on the semiconductor substrate having the trench oxidation-preventive film, and a sidewall spacer formed a sidewall of the gate line, wherein the trench oxidation-preventive film is disposed on the insulating material and disposed under the gate line and the sidewall spacer.Type: GrantFiled: July 21, 2003Date of Patent: May 31, 2005Assignee: Samsung Electronics Co., LTDInventor: Tai-Su Park
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Patent number: 6897485Abstract: A device for optical and/or electrical data transmission and/or processing has at least one electrical component, at least one optoelectronic component electrically connected to the electrical component, and an optically transparent carrier with a first surface, on which the electrical component and the optoelectronic component are disposed. Light is coupled into or out of the optoelectronic component through the carrier, and a frame is connected to the carrier, via which frame the components disposed on the carrier are electrically contact-connected. The device provides both optical and electrical inputs and outputs for optoelectronic and electrical components integrated into a device.Type: GrantFiled: June 17, 2003Date of Patent: May 24, 2005Assignee: Infineon Technologies AGInventor: Jörg-Reinhardt Kropp
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Patent number: 6897567Abstract: A method of making a semiconductor device is provided. The method includes the following steps. First, a semiconductor chip is mounted on a lower conductor, with first solder material applied between the chip and the lower conductor. Then, an upper conductor is placed on the chip, with second solder material applied between the chip and the upper conductor. Then, the first and the second solder materials are heated up beyond their respective melting points. Finally, the first and the second solder materials are allowed to cool down, so that the first solder material solidifies earlier than the second solder material.Type: GrantFiled: July 31, 2001Date of Patent: May 24, 2005Assignee: Romh Co., Ltd.Inventor: Yoshitaka Horie