Patents Examined by Eddie Lee
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Patent number: 7091544Abstract: A dynamic random access memory structure is provided, each active area of a memory unit cell is distributed individually in a substrate, and deep trench patterns are designed to have a checkerboard-like arrangement in the substrate. Also, there is a constant space between each deep trench pattern in a row. Further, long bit line contact plugs are located to electrically connect active areas of two diagonally neighbor memory unit cells, and a contact hole is formed on each long bit line contact plug to enable bit lines contact the long bit line contact plugs so two diagonally neighbor memory unit cells are controlled by the same bit line.Type: GrantFiled: November 4, 2004Date of Patent: August 15, 2006Assignee: Promos Technologies Inc.Inventors: Rui-Yuan Hon, Tony Chien
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Patent number: 7091554Abstract: A semiconductor device with high turn off capability includes a plurality of stripe trench lines which are provided in each of adjacent cell regions of a semiconductor layer in parallel and extended from one cell region toward the other cell region, a gate insulating film formed in each of the trench lines, and a gate electrode embedded in each of the trench lines with the gate insulating film interposed therebetween. In this semiconductor device, in each of the cell regions, part of adjacent ends of the plurality of trench lines on a side of the other cell region are connected to each other by connecting portions, and portions between the remaining adjacent ends are open. Moreover, at least one of the connecting portions of one cell region faces one of the open portions of the other cell region.Type: GrantFiled: December 22, 2003Date of Patent: August 15, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Hiroki Muraoka, Hidetoshi Nakanishi, Tetsujiro Tsunoda, Shinichi Umekawa
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Patent number: 7084474Abstract: A photosensitive semiconductor package and a method for fabricating the same are proposed. The package includes a carrier having a first surface, an opposite second surface, and an opening penetrating the carrier; a photosensitive chip having an active surface and a non-active surface, wherein a plurality of bond pads are formed close to edges of the active surface, and the chip is mounted via corner positions of its active surface to the second surface of the carrier, with the bond pads being exposed via the opening; a plurality of bonding wires formed in the opening, for electrically connecting the bond pads of the chip to the first surface of the carrier; a light-penetrable unit attached to the active surface of the chip and received in the opening; and an encapsulant for encapsulating the bonding wires and peripheral sides of the chip to seal the opening.Type: GrantFiled: October 5, 2004Date of Patent: August 1, 2006Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chia-Yu Hung, Chien-Ping Huang, Ke-Chuan Yang
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Patent number: 7081661Abstract: In the high-frequency module of the present invention, an insulating resin is formed so as to seal a high-frequency semiconductor element mounted on a surface of a substrate and further to seal electronic components. Furthermore, a metal thin film is formed on the surface of the insulating resin. This metal thin film provides an electromagnetic wave shielding effect.Type: GrantFiled: March 13, 2002Date of Patent: July 25, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hideki Takehara, Noriyuki Yoshikawa, Kunihiko Kanazawa
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Patent number: 7078820Abstract: A process of production of a semiconductor apparatus which can suppress a rise in the electrical resistance and a decline in the joint strength at the bump connection interfaces and improve the connection reliability when using the method of reinforcing the bases of the bumps by a resin film. Bumps are formed on a semiconductor wafer formed with a pattern circuit of a semiconductor chip so as to connect to the circuit pattern, a resin film is formed on the bump forming surface of the semiconductor wafer to a thickness giving a surface lower than the height of the bumps while sealing the spaces between the bumps, plasma cleaning etc., is used to remove the sealing resin components deposited on the surface portions of the bumps or natural oxides or other insulating impurities to clean and activate the surfaces of the bumps, and the chip is mounted on a mounting board.Type: GrantFiled: July 25, 2001Date of Patent: July 18, 2006Assignee: Sony CorporationInventor: Toshiharu Yanagida
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Patent number: 7078742Abstract: A strained-channel semiconductor structure and method of fabricating the same. The strained-channel semiconductor structure comprises a substrate composed of a first semiconductor material with a first natural lattice constant. A channel region is disposed in the substrate and a gate stack is disposed over the strained channel region A pair of source/drain regions are oppositely disposed in the substrate adjacent to the channel region, wherein each of the source/drain regions comprises a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant rather than the first natural lattice constant, an inner side and an outer side corresponding to the gate stack, and at least one outer sides laterally contacts the first semiconductor material of the substrate.Type: GrantFiled: September 4, 2003Date of Patent: July 18, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Chieh Lin, Yee-Chia Yeo
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Patent number: 7075124Abstract: A radiation-sensitive semiconductor body which has at least one radiation-absorbent active area (2) between at least two contact layers (6, 7) and which receives electromagnetic radiation in a wavelength range between ?1 and ?2 where ?2>?1. A filter layer (5) is arranged between the active area (2) and a radiation input surface (9). The active area (2) detects electromagnetic radiation at a wavelength below ?2. The filter layer (5) absorbs electromagnetic radiation at a wavelength below ?1, and passes electromagnetic radiation at a wavelength above ?1.Type: GrantFiled: July 30, 2004Date of Patent: July 11, 2006Assignee: Osram Opto Semiconductors GmbHInventors: Tony Albrecht, Peter Brick, Glenn-Yves Plaine, Marc Philippens
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Patent number: 7075142Abstract: A cell array of a flash memory device includes extended source strapping regions. The cell array includes a device isolation layer and active regions. The device isolation layer is formed in a semiconductor substrate, and the active regions are defined by the device isolation layer. Word lines cross over the active regions, and a common source line electrically connects the active regions between two word lines of word line pairs. A source strapping region is defined between the two word lines of the word line pairs. The source strapping region crosses multiple active regions.Type: GrantFiled: November 15, 2004Date of Patent: July 11, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-pil Sim, Chan-kwang Park
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Patent number: 7071111Abstract: The present invention relates to an integrated circuit having a sealed nitride layer. In one embodiment, a method of forming a sealing nitride layer overlaying a silicon oxide layer in a contact opening of an integrated circuit is disclosed. The method comprises, forming a second layer of nitride overlaying a first layer of nitride to form the sealing nitride layer. The second layer of nitride further overlays an exposed portion of a surface of a substrate in the contact opening and sidewalls of the contact opening. Using reactive ion etching (RIE etch) without a mask to remove a portion of the second nitride layer adjacent the surface of the substrate in the contact opening to expose a portion of the surface of the substrate in the contact opening without removing portions of the second nitride layer covering the sidewalls of the contact opening.Type: GrantFiled: October 25, 2001Date of Patent: July 4, 2006Assignee: Intersil Americas Inc.Inventor: James D. Beasom
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Patent number: 7071523Abstract: A semiconductor module that includes a resin package having a first surface and a second surface which is different from the first surface. A lead includes an inner portion covered by the resin package and an outer portion projecting from the first surface of the resin package. A semiconductor element is mounted to the inner portion of the lead and is covered by the resin package. A conductive film, provided separately from the lead, covers at least the second surface of the resin package, with the conductive film provided with a connecting portion held in contact with the outer portion of the lead at the first surface of the resin package. The inner portion of the lead includes an extension extending toward the second surface of the resin package the extension being held in contact with the conductive film at the second surface of the resin package.Type: GrantFiled: July 27, 2004Date of Patent: July 4, 2006Assignee: Rohm Co., Ltd.Inventors: Shinji Yano, Naoki Kumura, Tetsuya Yamasaki
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Patent number: 7067847Abstract: On a substrate made of e.g., sapphire single crystal is formed an Al underlayer having FWHM X-ray rocking curve value of 90 seconds or below. A buffer layer is formed on the AlN underlayer and has a composition of AlpGaqIn1?p?qN (0?p?1, 0?y?q). A GaN-based semiconductor layer group is formed on the buffer layer.Type: GrantFiled: December 14, 2001Date of Patent: June 27, 2006Assignee: NGK Isulators, Ltd.Inventors: Tomohiko Shibata, Keiichiro Asai, Yukinori Nakamura, Mitsuhiro Tanaka
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Patent number: 7064399Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).Type: GrantFiled: September 7, 2001Date of Patent: June 20, 2006Assignee: Texas Instruments IncorporatedInventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
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Patent number: 7061033Abstract: The invention provides a solid-state imaging device that include a pixel array where a plurality of unit pixels each including a photo diode and an insulated gate field effect transistor for detecting a photocharge are arranged, and a control circuit that controls the operation of the pixel array. The control circuit can apply a predetermined voltage to a source diffused region of the insulated gate field effect transistor and applies voltage by which a channel region becomes a conductive state to a gate electrode to bias a junction region formed of a semiconductor substrate of a first conductivity type and a semiconductor layer of a second conductivity type in a forward direction so as to accumulate a predetermined amount of the charge of a predetermined conductivity type in an accumulation region, and thereby causing the charge of a predetermined conductivity type accumulated in the accumulation region to be discharged.Type: GrantFiled: February 19, 2004Date of Patent: June 13, 2006Assignee: Seiko Epson CorporationInventor: Takashi Takamura
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Patent number: 7061084Abstract: A lead-bond type chip package includes a multilayer substrate for supporting and electrical interconnecting a semiconductor chip. The multilayer substrate has a slot defined therein. The multilayer substrate comprises an interlayer circuit board having prepregs disposed thereon, a plurality of leads on the prepreg on the upper surface of the interlayer circuit board, and a plurality of solder pads for making external electrical connection on the prepreg on the lower surface of the interlayer circuit board. The leads of the multilayer substrate are bonded to corresponding bonding pads formed on the semiconductor chip. A package body is formed on the multilayer substrate around the semiconductor chip and in the slot of the multilayer substrate. The multilayer substrate is capable of providing a power or ground plane formed therein for enhancing the electrical performance of the package, and providing a high wiring density for packaging a chip with high I/O connections.Type: GrantFiled: September 5, 2003Date of Patent: June 13, 2006Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Kun-Ching Chen, Yung I Yeh
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Patent number: 7057242Abstract: An integrated circuit transistor includes an active region in a substrate, elongated along a first direction. A gate pattern is disposed on the substrate and crosses the active region along a second direction transverse to the first direction. The gate pattern includes an access gate portion disposed on the active region and narrowed at a central portion thereof. The gate pattern may further include a pass gate portion adjoining the access gate portion at the point beyond the edge of the active region, the pass gate portion having a lesser extent along the first direction than the access gate portion.Type: GrantFiled: October 3, 2002Date of Patent: June 6, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-young Kim, Hyoung-sub Kim
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Patent number: 7057292Abstract: A solder bar compatible with conventional flip chip technology fabrication methods for high power/high current applications includes first and second generally circular solder pads of diameter D formed upon a substrate and connected by a solder bar pad of width BW. The centers of the generally circular solder pads are spaced apart by distance BL (bar length). A mass of solder having volume VB is formed over the first and second generally circular solder pads and over the solder bar pad to form a dog-bone shaped solder bar. The solder bar reaches height H1 above the centers of the first and second generally circular solder pads, and reaching height H2 above the midpoint of the solder bar pad. The values for diameter D, bar length BL, bar width BW, and solder volume VB are selected in such manner that H1 and H2 are approximately equal.Type: GrantFiled: May 19, 2000Date of Patent: June 6, 2006Assignee: FlipChip International, LLCInventors: Peter Elenius, Hong Yang
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Patent number: 7053456Abstract: An electronic component includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a cavity that penetrates from the first surface to the second surface of the semiconductor substrate, and an electrical mechanical element that has a movable portion formed above the first surface of the semiconductor substrate so that the movable portion is arranged above the cavity. The electronic component further includes an electric conduction plug, which penetrates from the first surface to the second surface of the semiconductor substrate, and which is electrically connected to the electrical mechanical element.Type: GrantFiled: June 2, 2004Date of Patent: May 30, 2006Assignee: Kabushiki Kaisha ToshibaInventor: Mie Matsuo
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Patent number: 7049185Abstract: In a semiconductor device including active areas where transistors are formed and a field area for isolating the active areas from each other, the field area has a plurality of dummy areas where dummy gates are formed.Type: GrantFiled: December 12, 2000Date of Patent: May 23, 2006Assignee: NEC Electronics CorporationInventor: Kazuyuki Ito
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Patent number: 7045862Abstract: A field effect transistor (FET) comprising an isolation layer, a source region positioned over the isolation layer, a drain region positioned over the isolation layer, a bifurcated silicide gate region positioned over the channel region, and a gate oxide layer adjacent to the gate region, wherein the gate oxide layer comprises an alkali metal ion implanted at a dosage calculated based on threshold voltage test data provided by a post silicide electrical test conducted on said FET, wherein the alkali metal ion comprises any of cesium and rubidium.Type: GrantFiled: June 11, 2004Date of Patent: May 16, 2006Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak
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Patent number: 7030443Abstract: A MIM (metal-insulator-metal) capacitor is provided with a substrate; a first metal area; a second metal area formed between the substrate and the first metal area; and a first insulating layer formed between the first metal area and the second metal area; wherein a capacitance value is determined by opposing surface areas of the first metal area and the second metal area; and the MIM capacitor is further provided with: a third metal area formed between the second metal area and the substrate; and a second insulating layer formed between the third metal area and the second metal area; wherein the third metal area is connected to a ground potential.Type: GrantFiled: September 1, 2003Date of Patent: April 18, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takuo Hino, Yoshihisa Minami