Abstract: In a conventional method of crystallization using a laser beam, variance (or dispersion) in a TFT characteristic becomes large, which causes various functions of a semiconductor device comprising TFTs as components of its electronic circuit to be restrained. A first shape of semiconductor region having on its one side a plurality of sharp convex top-end portions is formed first and a continuous wave laser beam is used for radiation from the above region so as to crystallize the first shape of semiconductor region. A continuous wave laser beam condensed in one or plural lines is used for the laser beam. The first shape of semiconductor region is etched to form a second shape of semiconductor region in which a channel forming region and a source and drain region are formed. The second shape of semiconductor region is disposed so that a channel forming range would be formed on respective crystal regions extending from the plurality of convex end portions.

Abstract: The present invention relates to a ferroelectric polymer storage device including at least two stacked ferroelectric polymer memory structures that are arrayed next to at least two respective stacked topologies that are a pre-fabricated silicon substrate cavity that includes interlayer dielectric layers and via structures.

Abstract: A phase changing memory device, and method of making the same, that includes contact holes formed in insulation material that extend down to and exposes source regions for adjacent FET transistors. Spacer material is disposed in the holes with surfaces that define openings each having a width that narrows along a depth of the opening. Lower electrodes are disposed in the holes. A layer of phase change memory material is disposed along the spacer material surfaces and along at least a portion of the lower electrodes. Upper electrodes are formed in the openings and on the phase change memory material layer. For each contact hole, the upper electrode and phase change memory material layer form an electrical current path that narrows in width as the current path approaches the lower electrode, such that electrical current passing through the current path generates heat for heating the phase change memory material disposed between the upper and lower electrodes.

Abstract: In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.

Abstract: The present invention is directed to organic photosensitive optoelectronic devices and methods of use for determining the position of a light source. Provided is an organic position sensitive detector (OPSD) comprising: a first electrode, which is resistive and may be either an anode or a cathode; a first contact in electrical contact with the first electrode; a second contact in electrical contact with the first electrode; a second electrode disposed near the first electrode; a donor semiconductive organic layer disposed between the first electrode and the second electrode; and an acceptor semiconductive organic layer disposed between the first electrode and the second electrode and adjacent to the donor semiconductive organic layer. A hetero-junction is located between the donor layer and the acceptor layer, and at least one of the donor layer and the acceptor layer is light absorbing.

Abstract: A method for forming a semiconductor wafer such as a standard semiconductor wafer used in a surface analysis system. Openings may be formed by partially etching a semiconductor substrate, and an insulation film may be formed on the openings. Contact holes may be formed to expose portions of the semiconductor substrate and the insulation film in the openings. The contact holes may be inspected by the surface analysis system, and the reliability of data obtained from the surface analysis system may be more precisely discriminated.

Abstract: A light emitting element containing an organic compound has a disadvantage in that it tends to be deteriorated by various factors, so that the greatest problem thereof is to increase its reliability (make longer its life span). The present invention provides a method for manufacturing an active matrix type light emitting device and the configuration of such an active matrix type light emitting device having high reliability. In the method, a contact hole extending to a source region or a drain region is formed, and then an interlayer insulation film made of a photosensitive organic insulating material is formed on an interlayer insulation film. The interlayer insulation film has a curved surface on its upper end portion. Subsequently, an interlayer insulation film provided as a silicon nitride film having a film thickness of 20 to 50 nm is formed by a sputtering method using RF power supply.

Abstract: The present invention discloses a mask ROM which has excellent compatibility with a logic process and improves integration of a memory cell, and a fabrication method thereof. The mask ROM includes: a substrate where a memory cell array region and a segment select region are defined; first and second trenches respectively formed at the outer portion of the memory cell array region and at the outer portion of a buried layer formation region of the segment select region; an element isolating film and an isolating pattern respectively filling up the first and second trenches; a plurality of buried layers aligned on the substrate in a first direction by a predetermined interval, and surrounded by the isolating pattern; and a plurality of gates aligned in a second direction to cross the buried layers in an orthogonal direction.

Abstract: First standard cells with no contact pattern and second standard cells having first contact patterns are placed on an area where a cell array is to be formed. Second contact patterns are additionally placed between the first standard cells. The second contact patterns are placed in an area that lacks a power supply capability.

Abstract: A semiconductor device in certain embodiments includes an insulating layer provided above the upper surface of a semiconductor substrate, and a capacitive element section and a resistance element section formed above the insulating layer. In the capacitive element section, a gate electrode serving as an opposite electrode for the capacitive element is formed above the insulating layer. The gate electrode is covered with a dielectric layer comprising silicon oxide, silicon nitride or tantalum oxide, and an electrode for the capacitive element comprising MoSix is provided above the dielectric layer. The resistance element section has a resistance element comprising MoSix formed simultaneously with the electrode for the capacitive element in the same process.

Abstract: An LDMOS transistor and a bipolar transistor with LDMOS structures are disclosed for suitable use in high withstand voltage device applications, among others. The LDMOS transistor includes a drain well region 21 formed in P-type substrate 1, and also formed therein spatially separated one another are a channel well region 23 and a medium concentration drain region 24 having an impurity concentration larger than that of drain well region 21, which are simultaneously formed having a large diffusion depth through thermal processing. A source 11s is formed in channel well region 23, while a drain 11d is formed in drain region 24 having an impurity concentration larger than that of drain region 24. In addition, a gate electrode 11g is formed over the well region, overlying the partially overlapped portions with well region 23 and drain region 24 and being separated from drain 11d.

Abstract: A flat lamp for emitting light to a surface area of a liquid crystal display device includes a bottom having a channel uniformly crossing an entire surface of the bottom, an arc-discharging gas is disposed within the channel, a cover disposed upon an upper junction surface of the bottom, the cover is coated with a fluorescent material, and an electric field generating means for generating an electric field, wherein the electric field generating means is placed along opposing lateral sides of the channel.

Abstract: The present invention relates to a Fine Pitch flip chip substrate. A black oxide dam is made on the metal circuit between bump pads to replace the conventional solder resist so that the bump pads will not be buried in the solder resist. A small via is drilled by laser drilling and plated filled with copper to be used as the connection between the circuits. By this way, the density and the flexibility of routing could be improved. A mesh pattern can be made in the limited space to increase the stiffness of the substrate.

Abstract: Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The gate bus trench and/or gate structures in the device trenches can contain a metal/silicide to reduce resistance, where polysilicon layers surround the metal/silicide to prevent metal atoms from penetrating the gate oxide in the device trenches. CMP process can remove excess polysilicon and metal and planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.

Abstract: The invention provides an elevated photodiode for image sensors and methods of formation of the photodiode. Elevated photodiodes permit a decrease in size requirements for pixel sensor cells while reducing leakage, image lag and barrier problems typically associated with conventional photodiodes.

Abstract: There is provided a semiconductor device having TFTs whose thresholds can be controlled. There is provided a semiconductor device including a plurality of TFTs having a back gate electrode, a first gate insulation film, a semiconductor active layer a second gate insulation film and a gate electrode, which are formed on a substrate, wherein an arbitrary voltage is applied to the back gate electrode.

Abstract: An integrated circuit, comprising: a predefined block of functional circuitry having a plurality of I/O pins; and a backside I/O pad electrically connected to each I/O pin through a backside via of the integrated circuit.

Abstract: A method for producing a semiconductor component with adjacent Schottky (5) and pn (9) junctions positions in a drift area (2, 10) of a semiconductor material. According to the method, a silicon carbide substrate doped with a first doping material of at least 1018 cm?3 is provided, and a silicon carbide layer with a second doping material of the same charge carrier type in the range of 1014 and 1017 cm?3 is homo-epitaxially deposited on the substrate. A third doping material with a complimentary charge carrier is inserted, and structured with the aid of a diffusion and/or ion implantation, on the silicon carbide layer surface that is arranged far from the substrate to form pn junctions. Subsequently the component is subjected to a first temperature treatment between 1400° C. and 1700° C. Following this temperature treatment, a first metal coating is deposited on the implanted surface in order to form a Schottky contact and then a second metal coating is deposited in order to form an ohmic contact.

Abstract: A semiconductor device is provided which includes a first semiconductor chip, a substrate onto which the first semiconductor chip is flip-chip bonded and on which a concave is formed along one side of the first semiconductor chip which is flip-chip bonded, a second semiconductor chip which is flip-chip bonded onto a portion on the substrate opposite the first semiconductor chip across the concave on the substrate, and a resin applied to spaces between the substrate and the first and second semiconductor chips.

Abstract: As disclosed herein, an electrostatic discharge (ESD) protection circuit is provided for an integrated circuit including a semiconductor substrate. The ESD protection circuit includes a plurality of active devices formed in the semiconductor substrate, the active devices being formed by a process including a plurality of steps carried out to form, at the same time, a plurality of active devices having a function other than ESD protection. For example, the ESD circuit may include an array of vertical transistors formed according to a process including many of the steps used to form, at the same time, vertical transistors of a DRAM array. Also disclosed is the formation of an ESD circuit in an “unusable” area of a semiconductor chip, such as under a bond pad, land or under bump metallization of the chip.