Abstract: This invention relates to a method of forming a bottomless liner structure. The method involves the steps of first obtaining a material having a via. Next, a first layer is deposited on the material, the first layer covering the sidewalls and bottom of the via. Finally, a second layer is sputter deposited on the first material, the material Rf biased during at least a portion of the time that the second layer is sputter deposited, such that the first layer deposited on the bottom of the via is substantially removed and substantially all of the first layer deposited on the sidewalls of the via is unaffected.

Abstract: A bitline contact and method of forming bitline contact for a vertical DRAM array using a bitline contact mask. In the method, gate conductor lines are formed. An oxide layer is deposited over the gate conductor lines, and a bitline contact mask is formed over portions of the oxide layer. The bitline contact mask is etched, and a silicon layer is deposited on the substrate. A bitline layer is deposited on the silicon layer. A masking and etching operation is performed on the bitline layer. A M0 metal is deposited over the silicon layer and on sides of non etched portions of the bitline (M0) layer to form left and right bitlines.

Abstract: A packaged die (112) for an integrated circuit (62) that eliminates the wire bonds required in the prior art, and provides integrated circuit packaging while the circuit (62) is still in a wafer format. A wafer substrate (64) on which the integrated circuits (62) have been fabricated is patterned and etched to form signal and ground vias (74, 72) through the substrate (64). A back-side ground plane (82) is deposited in contact with the ground vias (72). A protective layer (90) is formed on the top surface (76) of the substrate (64), and a protective layer (98) is formed on the bottom surface (84) of the substrate (64), where the bottom protective layer (98) fills in removed substrate material between the integrated circuits (62). Vias (106) are formed through the bottom protective layer (98), and the wafer substrate (64) is diced between the integrated circuits (62).

Abstract: A flat lamp for emitting light to a surface area of a liquid crystal display device includes a bottom having a channel uniformly crossing an entire surface of the bottom, an arc-discharging gas is disposed within the channel, a cover disposed upon an upper junction surface of the bottom, the cover is coated with a fluorescent material, and an electric field generating means for generating an electric field, wherein the electric field generating means is placed along opposing lateral sides of the channel.

Abstract: A semiconductor device having a capacitor of an MIM structure and a method of forming the same are described. The semiconductor device includes a semiconductor substrate; a first bottom interconnection formed over the semiconductor substrate; an intermetal dielectric layer formed over the semiconductor substrate; a plurality of openings exposing the first bottom interconnection through the intermetal dielectric layer; a bottom electrode conformally formed on the inside wall of the openings, on the exposed surface of the first bottom interconnection and on the intermetal dielectric layer between the openings; a dielectric layer and an upper electrode sequentially stacked on the bottom electrode; and a first upper interconnection disposed on the upper electrode. According to the present invention, an effective surface area per a unit planar area of a capacitor with an MIM structure is enlarged to increase capacitance thereof.

Abstract: A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.

Abstract: A ferroelectric liquid crystal display having alignment films with different surface polarities. The alignment films induce an internal electric field through the liquid crystal. Because of the induced internal electric field, initial liquid crystal alignment, and subsequent liquid crystal alignments, can be performed without an externally applied electric field.

Abstract: Memory elements, switching elements, and peripheral circuits to constitute a nonvolatile memory are integrally formed on a substrate by using TFTs. Since semiconductor active layers of memory element TFTs are thinner than those of other TFTs, impact ionization easily occurs in channel regions of the memory element TFTs. This enables low-voltage write/erase operations to be performed on the memory elements, and hence the memory elements are less prone to deteriorate. Therefore, a nonvolatile memory capable of miniaturization can be provided.

Abstract: Control of the characteristic impedance of wirings is performed with high accuracy.

Abstract: A method for forming an integrated circuit is provided. A semiconductor film is formed onto a first substrate. A metal film is formed onto a second substrate. The second substrate is bonded with the metal film onto the thin film of the first substrate. A first layer of transistors is formed onto the film. The second substrate is removed at a temperature within a low temperature range. The semiconductor film is bonded with the first layer of transistors onto a second layer of transistors of a third substrate.

Abstract: A frame for a semiconductor package includes plural lead frames arranged through grid-leads in a matrix. Semiconductor devices are mounted on individual lead frames of the frame, and are molded with molding compound. Thereafter, the molded semiconductor devices are cut at grid-leads by means of a dicing saw so that individual semiconductor packages are obtained. The frame further has groove portions which are formed by etching the frame from the front or back at areas corresponding to grid-leads, so that the grid-leads are made thin which reduces burrs and the generation of metal powders and dust.

Abstract: Disclosed is an ISFET comprising a H+-sensing membrane consisting of RF-sputtering a-WO3. The a-WO3/SiO2-gate ISFET of the present invention is very sensitive in aqueous solution, and particularly in acidic aqueous solution. The sensitivity of the present ISFET ranges from 50 to 58 mV/pH. In addition, the disclosed ISFET has high linearity. Accordingly, the disclosed ISFET can be used to detect effluent.

Abstract: A MOSFET includes a double silicided source/drain structure wherein the source/drain terminals include a silicided source/drain extension, a deep silicided source/drain region, and a doped semiconductor portion that surrounds a portion of the source/drain structure such that the suicides are isolated from the MOSFET body node. In a further aspect of the present invention, a barrier layer is formed around a gate electrode to prevent electrical shorts between a silicided source/drain extension and the gate electrode. A deep source/drain is then formed, self-aligned to sidewall spacers that are formed subsequent to the silicidation of the source/drain extension.

Abstract: A semiconductor light receiving element having a light receiving layer (1) formed from a GaN group semiconductor, and an electrode (2) formed on one surface of the light receiving layer as a light receiving surface (1a) in such a way that the light (L) can enter the light receiving layer is provided. When the light receiving element is of a Schottky barrier type, the aforementioned electrode (2) contains at least a Schottky electrode, which is formed in such a way that, on the light receiving surface (1a), the total length of the boundary lines between areas covered with the Schottky electrode and exposed areas is longer than the length of the outer periphery of the light receiving surface (1a).

Abstract: A local oscillation FET has a source connecting pad, a drain connecting pad and a gate connecting pad. The source connecting pad occupies one corner of a substrate, and the drain and gate connecting pads are placed at the neighboring corners so that the three connecting pads form an L shape on the substrate. As a modification to this configuration, another source connecting pad is placed at the remaining corner of the substrate so that the drain and gate connecting pads are shielded from each other by the two source connecting pads. These device configurations contribute to size reduction of the local oscillation FET.

Abstract: A masking and etching technique during the formation of a memory cell capacitor which simultaneously separates storage poly into individual storage poly nodes and etches recesses into the storage poly nodes which increase the surface area of the storage poly nodes and thereby increase the capacitance of a completed memory cell without additional processing steps.

Abstract: A double diffused MOS (DMOS) transistor structure is provided that uses a trench trough suitable for high-density integration with mixed signal analog and digital circuit applications. The DMOS device can be added to any advanced CMOS process using shallow trench isolation by adding additional process steps for trench trough formation, a trench implant and a P-body implant. The trench trough and trench implant provide a novel method of forming a drain extension for a high-voltage DMOS device.

Abstract: In a ferroelectric transistor containing two source/drain zones with a channel region disposed there-between, a first dielectric intermediate layer containing Al2O3 is disposed on a surface of the channel region. A ferroelectric layer and a gate electrode are disposed above the first dielectric intermediate layer. The utilization of Al2O3 in the first dielectric intermediate layer results in the suppression of tunneling of compensation charges from the channel region into the first dielectric layer and thereby improves the time for data storage.

Abstract: A masking and etching technique during the formation of a memory cell capacitor which simultaneously separates storage poly into individual storage poly nodes and etches recesses into the storage poly nodes which increase the surface area of the storage poly nodes and thereby increase the capacitance of a completed memory cell without additional processing steps.

Abstract: A method of fabricating a field effect transistor with increased resistance to hot carrier damage is disclosed. An oxide is grown on the gate electrode. This oxide is strengthened by nitridation and anneal. After a lightly doped drain implant, a second side oxide and a conformal nitride layer are deposited. Then, the conformal nitride is anisotropically etched to form spacers for masking a high dose drain implant. An NMOS transitor fabricated with this process has been found to be forty percent less susceptible to hot carrier damage than a conventional lightly doped drain process. Also, this process has proven to be more manufacturable than one in which the side oxide is nitrided and re-oxidized.