Abstract: The invention intends to provide a TFT having a gate insulating film which has a high dielectric withstand voltage and can ensure a desired carrier mobility in an adjacent semiconductor active film. A gate electrode and a semiconductor active film are formed on a transparent substrate with a gate insulating film, which is formed of two layered insulating films, held between them. The gate insulating film is made up of a first gate insulating film which improves a withstand voltage between the gate electrode and the semiconductor active film, and a second gate insulating film which improves an interface characteristic between the gate insulating film and the semiconductor active film. The first and second gate insulating films are each formed of a SiNx film. The optical band gap of the first gate insulating film has a value in the range of 3.0 to 4.5 eV, and the optical band gap of the second gate insulating film has a value in the range of 5.0 to 5.3 eV.

Abstract: A semiconductor device has at least one high-voltage and low-voltage transistor on a single substrate. The reliability of the high-voltage transistor is enhanced by performing a LDD implantation in only the high-voltage transistor prior to conducting an oxidation process to protect the substrate and gate electrode. After the oxidation process is performed, the low-voltage transistor is subjected to an LDD implantation process. The resultant semiconductor device provides a high-voltage transistor having a deeper LDD region junction depth than the low-voltage transistor, ensuring reliability and performance.

Abstract: A high-voltage device with improved punch through voltage. A semiconductor silicon substrate has a high-voltage device region on which a gate structure is patterned. A lightly doped region is formed in the substrate and lateral to the gate structure. A spacer is formed on the sidewall of the gate structure. A heavily doped region is formed in the lightly doped region and lateral to the spacer. A lateral distance is kept between the spacer and the heavily doped region.

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.

Abstract: A display may be formed of a plurality of abutted tiles, each tile contributing a portion of the overall displayed image. Optical elements may be selectively situated between pixels to improve the optical performance of the display. In some embodiments, these optical elements may facilitate the use of relatively thicker cover glasses over the display tiles.

Abstract: In a semiconductor device having memory cells and peripheral circuits, the memory cells and the peripheral circuits are formed on a semiconductor substrate. Source regions, drain regions and gate electrodes of MOS transistors in the peripheral circuits are comprised of a refractory metallic silicide layer. Gate electrodes of MOS transistors in the memory cells are comprised of the refractory metallic silicide. Source and drain regions of the MOS transistors in the memory cells are not comprised of the refractory metallic silicide layer.

Abstract: Thermo-mechanical stress on vias is reduced, thereby reducing related failures. This can be done by maintaining a via-to-metal area ratio at least as large as a predetermined value below which the additional stress on the vias does not significantly increase.

Abstract: The invention provides an electro-optical device that can include a pixel electrode, a thin-film transistor (TFT) including a semiconductor layer connected to the pixel electrode, and a data line and scanning line connected to the TFT. The scanning line can include a narrow part as a gate electrode facing a channel region in the semiconductor layer, and a wide part not facing the channel region. Such construction permits the electro-optical device to display high quality images by preventing light from impinging the TFT.

Abstract: Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The conductive gate structure forms gates in device trenches in an active device region and forms a gate bus in a gate bus trench. The gate bus trench that connects to the device trenches can be wide to facilitate forming a gate contact to the gate bus, while the device trenches can be narrow to maximize device density. CMP process can be used to planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.

Abstract: A CMOS transistor is provided having a relatively high breakdown voltage. The CMOS transistor includes an N-type epitaxial layer on a P-type substrate. Between the substrate and epitaxial layer are a heavily doped N-type buried layer and a heavily doped P-type base layer. An N-type sink region is proximate the edge of the NMOS region, and twin wells are in the area surrounded with the sink region. N+ source and drain regions are formed in respective wells. As the sink region is interposed between the drain and isolation regions, a breakdown occurs between the sink and isolation regions when a high voltage is applied. Twin wells are also formed in the PMOS region. P+ source and drain regions are formed in respective wells. As the N-type well surrounds the source and bulk regions, a breakdown occurs between a buried region and the isolation region when a high voltage is applied.

Abstract: The present invention is related to an array substrate for use in a liquid crystal display.

Abstract: A semiconductor device comprises a semiconductor substrate having first conductivity type, a trench capacitor, provided in the substrate, having a charge accumulation region, a gate electrode provided on the substrate via a gate insulating film, a gate side wall insulating film provided on a side surface of the gate electrode, drain and source regions, provided in the substrate, having a second conductivity type, an isolation insulating film provided adjacent to the trench capacitor in the substrate to cover an upper surface of the charge accumulation region, a buried strap region having the second conductivity type, the buried strap region being provided to electrically connect an upper portion of the charge accumulation region to the source region in the substrate, and a pocket implantation region having the first conductivity type, the pocket implantation region being provided below the drain and source regions and being spaced apart from the strap region.

Abstract: Disclosed is an organic gate insulating film and an organic thin film transistor using the same, in which a photo-alignment group is introduced into an organic insulating polymer, so that an organic active film has superior alignment, thereby increasing mobility. Further, the organic active film has a larger grain size, enhancing transistor characteristics.

Abstract: A semiconductor device includes a MOS transistor, an interlayer insulating film, a contact plug, a capacitor lower electrode, a ferroelectric film and two capacitor upper electrodes. The MOS transistor is formed on a semiconductor substrate. The interlayer insulating film covers the MOS transistor. The contact plug is connected to an impurity diffusion layer of the MOS transistor. The capacitor lower electrode is formed on the contact plug. The two capacitor upper electrodes are formed on the capacitor lower electrode with the ferroelectric film interposed therebetween. A contact area between the contact plug and the capacitor lower electrode is greater than a contact area between each of the two capacitor upper electrodes and the ferroelectric film. At least a part of a gate electrode of the MOS transistor is located just below a region of the contact plug, which region is in contact with the capacitor lower electrode.

Abstract: The invention provides an elevated photodiode for image sensors and methods of formation of the photodiode. Elevated photodiodes permit a decrease in size requirement for pixel sensor cells while reducing leakage, image lag and barrier problems typically associated with conventional photodiodes.

Abstract: To provide a continuous oscillation laser apparatus, and a manufacturing method of a semiconductor device using the continuous oscillation laser apparatus, which can enhance processing efficiency. A laser apparatus according to the present invention includes: a laser oscillation apparatus; a unit for rotating an object to be processed; a unit for moving the object to be processed toward a center of the rotation or toward an outside from the center; and an optical system for processing a laser light outputted from the laser oscillation apparatus and irradiating the processed laser light to a definite region in a moving range of the object to be processed, in which, while the object to be processed is rotated, the object to be processed is moved toward the center of the rotation or toward the outside from the center to move a position where the definite region and the object to be processed overlap.

Abstract: A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than that of the buried regions. Therefore, since avalanche breakdown occurs in an active region, causing an avalanche breakdown current to flow through the active region having a large area, current concentration does not occur. As a result, a ruggedness of an element against breakdown is increased.

Abstract: In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.

Abstract: As a structure capable of housing a recording/reproducing unit within a thin type image display apparatus without damaging the characteristic of the thin-type image display apparatus such as a wall-hung TV when using the unit, there is provided an image display apparatus having a flat display panel and a casing that supports the display panel wherein a recording/reproducing unit that houses a storage medium therein and conducts the writing or reading with respect to the storage medium is supported substantially in parallel with the display panel within the casing. The image display apparatus is capable of changing the arrangement direction of the storage medium, suppressing an interference of the storage medium with a peripheral device at the time of projecting the storage medium, and housing the storage medium so as not to be superimposed on the display panel.

Abstract: A semiconductor device and a process for production thereof, said semiconductor device having a new electrode structure which has a low resistivity and withstands heat treatment at 400° C. and above. Heat treatment at a high temperature (400-700° C.) is possible because the wiring is made of Ta film or Ta-based film having high heat resistance. This heat treatment permits the gettering of metal element in crystalline silicon film. Since this heat treatment is lower than the temperature which the gate wiring (0.1-5 &mgr;m wide) withstands and the gate wiring is protected with a protective film, the gate wiring retains its low resistance.