Abstract: A short-channel NMOS transistor in a p-well, bordered laterally on each side by an isolation region and vertically by a channel stop region, has a n-source and a n-drain, each comprising a shallow region extending to the transistor gate and a deeper region recessed from the gate, and both having a depletion region when reverse biased. The shallow regions are surrounded in part by an enhanced p-doping implant pocket. The transistor further has in these regions of enhanced p-doping another region of a p-resistivity higher than the remainder of the semiconductor. These regions extend laterally approximately from the inner border of the respective shallow region to the inner border of the respective recessed region, and vertically from a depth just below the depletion regions of source and drain to approximately the top of the channel stop regions.

Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.

Abstract: A lithographic pattern includes a first scribe along an edge of a die region, and a second scribe along an opposing edge of the die region. The first scribe includes at least a first translucent box and a second translucent box. The second scribe includes at least a first opaque box and a second opaque box defined respectively by a first translucent frame and a second translucent frame. When the lithographic pattern is stepped between fields on a wafer, the first translucent box is placed at least partially within the first opaque box, and the second translucent box is placed at least partially within the second opaque box. If a continuous ring is formed from a pair of a translucent box and an opaque box, the fields are aligned at least within an amount equal to the difference between the dimensions of that translucent box and that opaque box divided by 2.

Abstract: A semiconductor device has a structure in which an impurity diffusion region with an impurity concentration lower than an impurity concentration of a source and a drain is formed between the source and drain and a channel below the gate, having an asymmetric shape with respect to a center line along which the gate extends.

Abstract: In a semiconductor device with a plurality of semiconductor chips stacked on a substrate, a wiring layer disposed so as to be sandwiched between the semiconductor chips, and a plurality of bonding pads, for connecting a bonding wire, provided on the wiring layer, are provided.

Abstract: Dopant of an n-type is deposited in the channel area of a p-type well of isolated gate floating gate NMOS transistors forming the memory cells of a memory device array connected in a NAND gate architecture. The dopant is provided by a tilt angle around the existing floating gate/control gate structure at the stage of the fabrication process where the floating gate/control structure is in existence, the field oxidation step may also have occurred, and implantation of the source and drain dopants may also have occurred. This forms a retrograde n-type distribution away from the direction of the surface of the substrate in the channel, which is also concentrated laterally toward the centerline axis of the gate structure and decreases towards the opposing source and drain regions. This deposition promotes buried-channel-like performance of the NMOS transistors connected in series in the NAND gate memory architecture.

Abstract: The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. In one aspect, the invention includes a method of forming a conductive line comprising: a) forming a polysilicon layer; forming a silicide layer against the polysilicon layer; b) providing a conductivity-enhancing impurity within the silicide layer; and c) providing the polysilicon layer and the silicide layer into a conductive line shape. In another aspect, the invention includes a programmable-read-only-memory device comprising: a) a first dielectric layer over a substrate; b) a floating gate over the first dielectric layer; c) a second dielectric layer over the floating gate; d) a conductive line over the second dielectric layer; and e) a metal-silicide layer over the conductive line, the metal-silicide layer comprising a Group III dopant or a Group V dopant.

Abstract: A semiconductor device includes a diffusion region in a semiconductor substrate, a gate insulation film on the semiconductor substrate, a gate electrode on the gate insulation film, an interlayer insulation film on the semiconductor substrate covering the gate electrode, and a capacitor on the interlayer insulation film. The capacitor includes a laminated structure made up of a lower electrode, a dielectric film, and an upper electrode. The diffusion region, the gate electrode, and the lower electrode are connected to one another by a common contact in the interlayer insulation film.

Abstract: A liquid crystal display panel (and a method for manufacturing the liquid crystal display panel) includes a gate line and a signal line intersecting the gate line at an intersection portion where the gate line and the signal line intersect each other. The gate line includes at least two conductive portions and at least one opening portion on the intersection portion.

Abstract: A multi-layer electrode (246) and method of fabrication thereof in which a conductive region (244) is separated from a barrier layer (222) by a first conductive liner (240) and a second conductive liner (242). First conductive layer (240) comprises Pt, and second conductive liner (242) comprises a thin layer of conductive oxide. The multi-layer electrode (246) prevents oxygen diffusion through the top conductive region (244) and reduces material variation during electrode patterning.

Abstract: A bipolar heterojunction transistor (HBT) includes a collector layer, a base layer formed on the collector layer, a first transition layer formed on the base layer, an emitter layer formed on the first transition layer, a second transition layer formed on the emitter layer, and an emitter cap layer formed on the second transition layer. Each of the first and second transition layers is formed of a composition that contains an element, the mole fraction of which is graded in such a manner that the conduction band of the HBT is continuous through the base layer, the first and second transition layers, the emitter layer and the emitter cap layer.

Abstract: A protective film for protecting a dielectric layer of a plasma display panel from discharge contains a metallic oxide. A volume resistivity of the protective film is 3.5×1011 &OHgr;·cm or more.

Abstract: A semiconductor chip having a plurality of flash memory devices, shallow trench isolation in the periphery region, and LOCOS isolation in the core region. A hard mask is used first to create the shallow trench isolation. The LOCOS isolation is then created. Subsequent etching is used to remove stringers. The flash memory is able to use shallow trench isolation to limit encroachment. The flash memory may also have a nitridated tunnel oxide barrier layer. A hard mask is used to prevent nitride contamination of the gate oxide layer. Periphery stacks have hate oxide layers of different thicknesses.

Abstract: The invention concerns a semi-conductor device comprising on a substrate: a first dynamic threshold voltage MOS transistor (10), with a gate (116), and a channel (111) of a first conductivity type, and a current limiter means (20) connected between the gate and the channel of said first transistor. In accordance with the invention, this first transistor is fitted with a first doped zone (160) of the first conductivity type, connected to the channel, and the current limiter means comprises a second doped zone (124) of a second conductivity type, placed against the first doped zone and electrically connected to the first zone by an ohmic connection. Application to the manufacture of CMOS circuits.

Abstract: Trenches for defining chip areas are formed on the surface of a semiconductor substrate so that outlines of side walls of each of the trenches have recesses or protrusions. Then, a sputtering film is so formed as to be continuous in an area bridging the surface of each of the chip areas and the inside surface of each of the trenches, and the semiconductor substrate is diced along lines outside the trenches.

Abstract: A semiconductor device in accordance with the present invention includes: an insulating layer; a semiconductor region formed on the insulating layer; a trench that surrounds side parts of the semiconductor region and reaches the insulating layer; an isolation insulating film formed in the trench; a semiconductor element in which the semiconductor region serves as an active region; a side oxide film formed by oxidizing the side parts of the semiconductor region and located between the rest of the semiconductor region and the isolation insulating film; and a bottom oxide film that is formed by oxidizing a bottom part of the semiconductor region, located over the entire interface between the rest of the semiconductor region and the insulating layer, and having side surfaces that reach the side oxide film.

Abstract: An aspect the present invention is to provide a semiconductor device including at least one MISFET structure having an element isolation region formed on a surface portion of a semiconductor substrate to have a closed region, an element region formed on the surface region of the semiconductor substrate to surround the element isolation region, a gate insulating film formed to cover at least the surface of the element region, a contact region formed on the element isolation region, and at least four gate electrodes connected to the contact region and formed on the surface of the element region via the gate insulating film to extend to at least outside the element region.

Abstract: A solid-state image pickup device in which no warp occurs in a solid-state image pickup element chip is provided. A solid-state image pickup device, including a solid-state image pickup element chip on which a plurality of solid-state image pickup elements are mounted, a wiring substrate electrically connected to the solid-state image pickup element chip and adapted to transmit signals from each one of a plurality of solid-state image pickup elements, and a protection cap provided on a light incident side of the solid-state image pickup element chip and adapted to protect the solid-state image pickup element chip, is characterized in that the solid-state image pickup element chip is formed on a substrate with a thermal expansion coefficient equal to that of the protection cap, and the substrate and the protection cap are sealed with a sealing resin.

Abstract: A small area cascode FET structure capable of operating at mm-wave frequenices cascades a common-source (CS) FET with a common gate (CG) FET, in a smaller physical area than conventional cascode FET structures. The small area of the cascode FET structure is partially achieved by using small source via grounds, requiring a thin gallium arsenide substrate (typically between 50 and 70 microns thick). The overall cascode area is reduced further, by having the two FETs share a common node. This common node is the output drain manifold of the CS FET, which is also an input source finger of the CG FET. In addition, small via grounds within the MIM capacitors and CS FET, which provide the ground connection to the gate manifolds of the CG FET, further reduce circuit area. Advantageously, the small area cascode FET can be applied to many different MMICs to reduce MMIC area requirements and cost.

Abstract: The present invention provides a capacitor formed in a dynamic random access memory (DRAM) semiconductor device, the capacitor comprising: a polysilicon layer to making contact with a diffusion region of an access device; a TiN comprising layer overlying the polysilicon layer; the TiN comprising layer and the polysilicon layer are patterned to serve as a bottom capacitor plate; a layer of dielectric material overlying the patterned TiN comprising layer; and a top capacitor plate. A method for forming the capacitor comprises the steps of: providing a opening to a diffusion region in an underlying substrate of a wordline activated transistor; forming a TiN comprising layer to make contact with the diffusion via the opening; patterning the TiN comprising layer into an individual bottom capacitor plate; forming a layer of dielectric material; and forming a top capacitor plate.