Patents Examined by Edward Dudek, Jr.
  • Patent number: 9329939
    Abstract: Provided is a two-way RAID controlled storage device of a serial attached small computer system interface/serial advanced technology attachment (SAS/SATA) type, which provides data storage/reading services through a PCI-Express interface. The RAID controller typically includes a plurality of disk mounts coupled disk connect controller, which itself is coupled to a set (e.g., at least one) of PCI-Express SSD memory disk units. In a typical embodiment, the plurality of PCI-Express SSD memory disk units comprising a plurality of volatile semiconductor memories. The RAID controller further comprises a plurality of disk monitoring units coupled to the plurality of disk mounts for monitoring the plurality of PCI-Express memory disk units; a plurality of disk plug and play controllers coupled to the plurality of disk monitoring units. A plurality of high-speed host interfaces are coupled to: the plurality of disk mounts, the plurality of disk monitoring units, and to a plurality of disk controllers.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: May 3, 2016
    Assignee: TAEJIN INFO TECH CO., LTD
    Inventor: Byungcheol Cho
  • Patent number: 9323675
    Abstract: Filtering snoop traffic in a multiprocessor computing system, each processor in the multiprocessor computing system coupled to a high level cache and a low level cache, the including: receiving a snoop message that identifies an address in shared memory targeted by a write operation; identifying a set in the high level cache that maps to the address in shared memory; determining whether the high level cache includes an entry associated with the address in shared memory; responsive to determining that the high level cache does not include an entry corresponding to the address in shared memory: determining whether the set in the high level cache has been bypassed by an entry in the low level cache; and responsive to determining that the set in the high level cache has not been bypassed by an entry in the low level cache, discarding the snoop message.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: April 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jason A. Cox, M V V Anil Krishna, Eric F. Robinson, Brian M. Rogers
  • Patent number: 9323668
    Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: April 26, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peter D. Driever, Charles W. Gainey, Jr., Steven G. Glassen, Thomas B. Mathias, Kenneth J. Oakes, Peter G. Sutton, Peter K. Szwed, Elpida Tzortzatos, Harry M. Yudenfriend
  • Patent number: 9325601
    Abstract: A method reduces a cycle time of an individual memory module to an effective cycle time shorter than the cycle time using a plurality of memory modules having a circular sequence. The method includes initiating a set of read operations on different memory modules of the plurality of memory modules in the circular sequence from a first read operation initiated on a first module of the plurality of memory modules to a last read operation initiated on the second module. After initiating each read operation of the set of read operations on a particular memory module of the plurality of memory modules and prior to initiating a next read operation in the set of read operations, the method initiates a set of write operations to write a same value to all of the plurality of memory modules in the circular sequence beginning one memory module after the particular memory module.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: April 26, 2016
    Assignee: Spirent Communications, Inc.
    Inventors: Craig Fujikami, Jocelyn Kunimitsu
  • Patent number: 9317211
    Abstract: A system and method for managing the life expectancy of at least one solid state drive (SSD) within a cache device of a storage subsystem includes determining a baseline rate of decline for each SSD based on its guaranteed life expectancy. At intervals, each SSD of the cache device is polled for remaining life and power-on time, and a current rate of decline (based on time since initialization) and a cumulative rate of decline (based on total lifespan of the SSD) is determined. When both the current rate of decline and the cumulative rate of decline exceed the baseline rate of decline for any SSD of the cache device, write requests to that SSD are blocked and redirected to the virtual device until either the current rate of decline or cumulative rate of decline drop below the baseline rate.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: April 19, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Sumanesh Samanta, Mohana Rao Goli, Karimulla Sheik
  • Patent number: 9318216
    Abstract: A multilevel cell (MLC) nonvolatile memory system including a plurality of memory cells each cell storing first bit data and second bit data, and a controller programming the plurality of memory cells on a page-by-page basis, the controller programming original data to an original block and programming copy data that is the same as the original data to a mirroring block, wherein first bit page data and second bit page data of the original data are programmed to memory cells connected to the same word line, but the first bit page data and second bit page data of the copy data are programmed to memory cells connected to different word lines.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: April 19, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Hee Ma, Da-Woon Jung, Byung-Hei Jun
  • Patent number: 9317216
    Abstract: A method, computer program product, and computing system for initiating a relocation process to move local data from an SMR-based storage tier within an auto-tiering data system to a different storage tier within the auto-tiering data system. The local data is located within one or more sectors of the SMR-based storage tier. The local data is copied from the SMR-based storage tier to the different storage tier. The one or more sectors of the SMR-based storage tier are unmapped.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: April 19, 2016
    Assignee: EMC Corporation
    Inventors: Walter A. O'Brien, Thomas E. Linnell
  • Patent number: 9317373
    Abstract: One or more snapshots of data stored over a period of time are maintained in a hybrid storage device comprising a magnetic disk and a solid state disk, wherein a selected snapshot stores information that allows recovery of data that is stored in the hybrid storage device at a selected point in time of the period of time. The hybrid storage device receives an input/output (I/O) command from a computational device. A category of a plurality of categories to which the I/O command belongs is determined, wherein the plurality of categories comprise writing to an unused block, writing to a used block, reading from an unused block, and reading from a used block. In response to determining the category to which the I/O command belongs, the I/O command is handled by one of the magnetic disk and the solid state disk based on the determined category.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: April 19, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhen X. Han, Scott R. Murray, Yi Tong, Rong Zhang, Xiao Q. Zhang
  • Patent number: 9311013
    Abstract: If a monitor measurement cycle is set as a long cycle, promotion in a short cycle cannot be performed; and even if the number of I/Os is very large in response to fluctuations of the number of I/Os in several minutes to several hours of normal work, pages will be promoted after waiting for several weeks. As a result, I/Os which could have normally accepted by an upper tier will be accepted by a lower tier, which results in a problem of worsening the performance efficiency. A monitoring system capable of preventing demotion due to temporary reduction of the number of I/Os for specific pages from a viewpoint of a long cycle and enabling prompt promotion in response to an increase of the number of U/Os for 3 the specific pages is realized. A load index value defined from a viewpoint of a long cycle and a load index value defined from a viewpoint of a short cycle are updated based on the number of I/Os which is counted cyclically for each storage area.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: April 12, 2016
    Assignee: HITACHI, LTD.
    Inventors: Hiroaki Akutsu, Yoshinori Ohira, Yoshiaki Eguchi, Masayuki Yamamoto
  • Patent number: 9311008
    Abstract: In accordance with the present disclosure, a system and method for performing a system memory save in tiered or cached storage during transition to a decreased power state is disclosed. As disclosed herein, the system incorporating aspects of the present invention may include a solid-state drive, volatile memory, and at least one alternate storage media. Upon transition to a decreased power state, at least some of the data in the solid-state drive may be transferred to the at least one alternate storage media. After the SSD data is transferred, data stored in volatile system memory, such as a system context, may be transferred to the SSD memory. With the system context saved in SSD memory, power to the volatile system memory may be turned off.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: April 12, 2016
    Assignee: Dell Products L.P.
    Inventors: William F. Sauber, Mukund P. Khatri
  • Patent number: 9304900
    Abstract: A data reading method, a memory controller, and a memory storage device are provided. The data reading method is adapted to a rewritable non-volatile memory module having a plurality of physical erasing units. The data reading method includes following steps. A plurality of logical addresses is configured to be mapped to a part of the physical erasing units. A plurality of read commands is received from a host system. The read commands instruct to read a plurality of first logical addresses among aforementioned logical addresses. The read commands are executed, and whether the first logical addresses are successive is determined. If the first logical addresses are successive, data belonging to a logical range is pre-read from the physical erasing units into a buffer memory. Thereby, the data reading speed is increased.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 5, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Shao-Hsien Liu
  • Patent number: 9305001
    Abstract: One or more techniques and/or systems are provided for generating a macroscopic cluster view of storage devices, as opposed to merely an isolated view from an individual node. For example, nodes within a node cluster may be queried for storage device reports comprising storage device information regarding storage devices with which the nodes are respectively connected (e.g., I/O performance statistics, path connections, storage device attributes, status, error history, etc.). The storage device reports may be aggregated together to define one or more storage device data structures (e.g., a storage device data structure comprising one or more tables that may be populated with storage device information). In this way, the cluster view may be generated based upon querying one or more storage device data structures (e.g., an error cluster view, a storage device cluster view, a node summary cluster view, etc.).
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: April 5, 2016
    Assignee: NetApp Inc.
    Inventors: Edward Barron, Loellyn Cassell, John DeGraaf
  • Patent number: 9298604
    Abstract: Described is using flash memory, RAM-based data structures and mechanisms to provide a flash store for caching data items (e.g., key-value pairs) in flash pages. A RAM-based index maps data items to flash pages, and a RAM-based write buffer maintains data items to be written to the flash store, e.g., when a full page can be written. A recycle mechanism makes used pages in the flash store available by destaging a data item to a hard disk or reinserting it into the write buffer, based on its access pattern. The flash store may be used in a data deduplication system, in which the data items comprise chunk-identifier, metadata pairs, in which each chunk-identifier corresponds to a hash of a chunk of data that indicates. The RAM and flash are accessed with the chunk-identifier (e.g., as a key) to determine whether a chunk is a new chunk or a duplicate.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: March 29, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sudipta Sengupta, Biplob Kumar Debnath, Jin Li
  • Patent number: 9298393
    Abstract: An intelligent write command routine improves the operational efficiency of a data storage device (DSD) by avoiding media access of the disk when a logical block address (LBA) and the physical sector are unaligned, thus reducing write time. When a write command is received by the DSD from the host, the intelligent write command routine maintains the read data of the read buffer, instead of clearing the read buffer and performing a read of the target sector on the disk per standard protocol. The intelligent write command copies the necessary adjacent sector data from the read buffer as a data patch to the write buffer to splice around the write data received with the write command. Following each write command, the data written to the disk in the write buffer is copied to the read buffer. The read buffer is maintained with the most current data on the disk and does not need to be flushed unless the LBA of the write command is beyond the data ranges stored in the read buffer.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: March 29, 2016
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: KokChoon See, Wesley Chan, CheeSeng Toh, PohGuat Bay, ChweeFern Ee, YongPeng Chng
  • Patent number: 9298638
    Abstract: Embodiments of the invention provide a method, system and computer program product for dynamic caching module selection for optimized data deduplication. In an embodiment of the invention, a method for dynamic caching module selection for optimized data deduplication is provided. The method includes receiving a request to retrieve data and classifying the request. The method also includes identifying from amongst multiple different caching modules each with a different configuration a particular caching module associated with the classification of the request. Finally, the method includes deduplicating the data in the identified caching module.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: March 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Robert D. Callaway, Ioannis Papapanagiotou
  • Patent number: 9298637
    Abstract: Embodiments of the invention provide a method, system and computer program product for dynamic caching module selection for optimized data deduplication. In an embodiment of the invention, a method for dynamic caching module selection for optimized data deduplication is provided. The method includes receiving a request to retrieve data and classifying the request. The method also includes identifying from amongst multiple different caching modules each with a different configuration a particular caching module associated with the classification of the request. Finally, the method includes deduplicating the data in the identified caching module.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Robert D. Callaway, Ioannis Papapanagiotou
  • Patent number: 9298608
    Abstract: The various implementations described herein include systems, methods and/or devices used to enable biasing for wear leveling in storage systems. In one aspect, the method includes (1) determining, for each erase unit of a plurality of erase units in the storage medium, an age metric, (2) determining a representative age metric of the plurality of erase units, (3) for each respective erase unit of the plurality of erase units, biasing a respective garbage collection control metric for the respective erase unit in accordance with the age metric of the respective erase unit in relation to the representative age metric of the plurality of erase units to generate an adjusted garbage collection control metric for the respective erase unit, and (4) performing garbage collection for the storage medium in accordance with the adjusted garbage collection control metrics of the plurality of erase units.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: March 29, 2016
    Assignee: SANDISK ENTERPRISE IP LLC
    Inventors: James Fitzpatrick, James Higgins
  • Patent number: 9292449
    Abstract: A cache memory data compression and decompression technique is described. A processor device includes a memory controller unit (MCU) coupled to a main memory and a cache memory. The MCU includes a cache memory data compression and decompression module that compresses data received from the main memory. The compressed data may then be stored in the cache memory. The cache memory data compression and decompression module may also decompress data that is stored in the cache memory. For example, in response to a cache hit for data requested by a processor, the compressed data in the cache memory may be decompressed and subsequently read or operated upon by the processor.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: March 22, 2016
    Assignee: Intel Corporation
    Inventors: Alaa R. Alameldeen, Niranjan L. Cooray, Jayesh Gaur, Steven D. Pudar, Manuel A. Aguilar Arreola, Margareth E. Marrugo, Chinnakrishnan Ballapuram
  • Patent number: 9292439
    Abstract: A method, device and computer program for efficiently identifying items having a high frequency of occurrence among items included in a large-volume text data stream. Identification information for identifying an item and a count of items are stored in a higher level of memory and only identification information is stored in a lower level. Text data stream input is received, the increment of the count of an item is increased in response to storage in the higher level memory of identification information for an item included in a bucket divided from the received text data stream input, identification information for the item is transferred with the initial count to the higher level of memory in response to storage in the lower level and the identification information for the item is newly stored with the initial count in the higher level in response to not being stored on any level.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Teruo Koyanagi, Takayuki Osogami, Raymond Harry Rudy
  • Patent number: 9280491
    Abstract: A first storage location at a memory management unit stores physical address information mapping logical physical addresses to actual physical addresses. A second storage location stores an allowed address range of actual physical addresses. A memory management unit determines whether a write access to the first storage location is allowable. The access is to store memory mapping information relating to a first actual physical address. The memory management unit prevents the write access if the first actual physical address is not in the allowed address range, and does not prevent the write access if the first actual physical address is in the allowed address range. The memory management unit prevents a write access to the second storage location by a process that is not running in a hypervisor mode.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: March 8, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Dov Levenglick