Abstract: A system and method of cache monitoring in storage systems includes storing storage blocks in a cache memory. Each of the storage blocks is associated with status indicators. As requests are received at the cache memory, the requests are processed and the status indicators associated with the storage blocks are updated in response to the processing of the requests. One or more storage blocks are selected for eviction when a storage block limit is reached. As ones of the selected one or more storage blocks are evicted from the cache memory, the block counters are updated based on the status indicators associated with the evicted storage blocks. Each of the block counters is associated with a corresponding combination of the status indicators. Caching statistics are periodically updated based on the block counters.

Abstract: Methods for managing data stored in a memory device facilitate managing utilization of memory of different densities. The methods include reading first data from a first number of pages or blocks of memory cells having a first density, performing a data handling operation on the read first data to generate second data, and writing the second data to a second number of pages or blocks of memory cells having a second density, wherein the second density is different than the first density, and wherein the second number is different than the first number.

Abstract: Methods, systems, and computer storage mediums including a computer program product method for formatting storage volumes are provided. One method includes creating a storage volume including a global counter and partitioned into multiple storage segments including a segment counter and partitioned into multiple stripes, wherein the global counter and each segment counter match at an initial time. The method further includes receiving a command to write data to a first stripe, comparing a first segment counter associated with the segment, determining if the segment and global counters match, and re-initializing first metadata associated with the segment to indicate the first segment requires formatting if the counters do not match. One system includes a processor for performing the above method and one computer storage medium includes a computer program product configured to perform the above method.

Abstract: A data processing apparatus has a memory rename table for storing memory rename entries each identifying a mapping between a memory address of a location in memory and a mapped register of a plurality of registers. The mapped register is identified by a register number. In response to a store instruction, the store target memory address of the store instruction is mapped to a store destination register and so the data value is stored to the store destination register instead of memory. A memory rename entry is provided in the table to identify the mapping between the store target memory address and store destination target register. In response to a load instruction, if there is a hit in the memory rename table for the load target memory address then the loaded value can be read from the mapped register instead of memory.

Abstract: The present invention discloses a memory card access device, the control method thereof and a memory card access system. Said device comprises: a memory card interface circuit to generate card-read data according to a card-read signal or generate a card-writing signal according to card-writing data; a host interface circuit to generate host-read data according to a host-read signal or generate the host-writing signal according to host-writing data; and a control circuit, coupled to the memory card and host interface circuits respectively, operable to generate the host-writing data by processing the card-read data according to a predetermined cache protocol or generating the card-writing data by processing the host-read data according to the predetermined cache protocol, so as to treat a memory card as a cache device.

Abstract: An apparatus and method are described for performing a cache line write back operation. For example, one embodiment of a method comprises: initiating a cache line write back operation directed to a particular linear address; determining if a dirty cache line identified by the linear address exists at any cache of a cache hierarchy comprised of a plurality of cache levels; writing back the dirty cache line to memory if the dirty cache line exists in one of the caches; and responsively maintaining or placing the dirty cache line in an exclusive state in at least a first cache of the hierarchy.

Abstract: A storage system and a method for realizing a storage system is disclosed, the storage system comprising: a disk array comprising at least one solid state disk and at least one non-solid state disk; and a storage control means configured to: in response to entering a scrubbing mode, scan and move data blocks in the at least one non-solid state disk in the disk array to form more continuous free blocks. The storage system of the present invention has good read and write performances, higher data reliability and availability, and lower cost.

Abstract: An information processing system that determines whether static data is already loaded into shared memory when a request is made to load static data into shared memory from a process out of a plurality of processes. When the information processing system determines that static data is not loaded into shared memory, after loading the data into shared memory, it notifies the requesting process with information identifying the static data. When the information processing system determines that the static data is already loaded into shared memory, it notifies the requesting process with information identifying the static data.

Abstract: A computer-implemented method for identifying access rate boundaries of workloads may include (1) tracking the number of times each region of data within a plurality of regions of data is accessed during a period of time, (2) creating an ordered list of each region of data from the plurality of regions of data, (3) calculating one or more drops in access rates between two or more regions of data in the ordered list, (4) determining that a calculated access-rate drop from a first region of data to a second region of data exceeds a predefined threshold, and (5) calculating a boundary access rate for a workload of data. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The embodiments described herein methods and devices that enhance the endurance of a non-volatile memory (e.g., flash memory). The method includes obtaining, for each of the plurality of die, an endurance metric. The method also includes sorting the plurality of die into a plurality of die groups based on their corresponding endurance metrics, where each die group includes one or more die and each die group is associated with a range of endurance metrics. In response to a write command specifying a set of write data, the method further includes writing the write data to the non-volatile memory by writing in parallel subsets of the write data to the one or more die assigned to a single die group of the plurality of die groups.

Abstract: A system and method for processing data stored in data storage devices is described. A computing processor acquires blocks of data from a target machine and computes an entropy value associated with each block of the acquired data. The computing processor checks the entropy values of each block to determine whether or not the particular block is deemed to contain useful data, before that block is analyzed.

Abstract: System and method embodiments are provided for coordinated hardware and software performance monitoring to determine a suitable polling time for memory cache during run time. The system and method adapt to the time-varying software workload by determining a next polling time based on captured local characteristics of memory access pattern over time. The adaptive adjustment of polling time according to system performance and dynamic software workload allows capturing more accurately the local characteristics of memory access pattern. An embodiment method includes capturing, at a current polling instance, hardware performance parameters to manage the memory cache, and adjusting a time interval for a next polling instance according to the hardware performance parameters. The captured hardware performance parameters are used to compute performance metrics, which are then used to determine the time interval for the next polling instance.

Abstract: A memory system may include a memory including a cell array having a plurality of word lines and an address storage unit that stores an address in response to a capture command, wherein the memory sequentially refreshes the word lines in response to a refresh command at a set cycle, and refreshes a word line corresponding to the stored address in response to the refresh command when the address is stored in the address storage unit; and a memory controller transmitting the refresh command to the memory at the set cycle when a word line satisfying one or more of conditions that the number of activation times is equal to or more than a reference number and an activation frequency is equal to or more than a reference frequency is detected, and transmitting the capture command and an address of the detected word line to the memory.

Abstract: Described is using flash memory, RAM-based data structures and mechanisms to provide a flash store for caching data items (e.g., key-value pairs) in flash pages. A RAM-based index maps data items to flash pages, and a RAM-based write buffer maintains data items to be written to the flash store, e.g., when a full page can be written. A recycle mechanism makes used pages in the flash store available by destaging a data item to a hard disk or reinserting it into the write buffer, based on its access pattern. The flash store may be used in a data deduplication system, in which the data items comprise chunk-identifier, metadata pairs, in which each chunk-identifier corresponds to a hash of a chunk of data that indicates. The RAM and flash are accessed with the chunk-identifier (e.g., as a key) to determine whether a chunk is a new chunk or a duplicate.

Abstract: A data storage area of a data storage device can be used to communicate information between the data storage device and an external device or software. In some examples, configuration data stored within the data storage area can be used to determine a subset of data to copy or move from a first data storage medium to a second data storage medium. The data storage area can be a unique partition and the data storage device can locate partition information to determine a location of the partition. The data storage device can then use the partition to store data for two-way communication between the data storage device and an external system, device, or software.

Abstract: Embodiments relate to saving data upon loss of power. An aspect includes sizing a write cache buffer based on parameters related to carrying out this emergency data save procedure. A computer implemented method for allocating a write cache on a storage controller includes retrieving, at run-time by a processor, one or more operating parameters of a component used in a power-loss save of the write cache. The component is selected from the group consisting of an energy storage element, a non-volatile memory, and a transfer logic. A size for the write cache on the storage controller is determined, based on the one or more operating parameters. A write cache, of the determined size, is allocated from a volatile memory coupled to the storage controller.

Abstract: Efficient techniques using a multi-port shared non-volatile memory are described that reduce latency in memory accesses from dedicated function specific processors, such as a modem control processor. The modem processor preempts a host processor that is accessing data from a multi-port shared non-volatile memory flash device allowing the modem processor to quickly access data in the flash device. The preemption process uses a doorbell interrupt initiated by a processor that seeks access and interrupts the processor being preempted. After preemption, the host processor may resume or restart the data access. Access control by the processors utilizes a hardware semaphore atomic control mechanism. Power control of the shared non-volatile memory modules includes at least one inactivity timer to indicate when a supply voltage to the shared non-volatile memory modules can be safely reduced or turned off. Power may be restarted by any of the processors sharing the memory, allowing fast access to the data.

Abstract: Various embodiments for managing data objects stored in a tiered data object storage environment, by a processor device, are provided. In one embodiment, a method comprises using an application to provide directives to the tiered data object storage environment for manipulating and managing stored data objects such that data objects with a pending management operation are refrained from being migrated from a higher storage tier to a lower storage tier.

Abstract: Various structures and methods are disclosed related to efficiently accessing a memory for a particular application. An embodiment of the present invention utilizes characteristics of an access pattern for a particular application to provide a more efficient organization of data in a memory. In one embodiment, the predictability in access needs for a particular application is exploited to provide a data organization method for organizing data in an SDRAM memory to support efficient access. In one embodiment, the particular application is operation under the Long Term Evolution (“LTE”) standard for wireless communications. In one embodiment, associated hardware and methods are provided to, when necessary, reorder read commands and, when necessary, reorder data read from memory so that at least some of the time overhead for accessing one row can be hid behind an access of another row.

Abstract: A method includes determining a plurality of configuration entries based on received provisioning requests and further based on provisioning system resource utilization data. Each configuration entry includes a corresponding virtual system template, and a corresponding number of virtual systems to be provisioned. The method also includes provisioning the corresponding number of virtual systems for a first configuration entry in the plurality of configuration entries. The corresponding number of virtual systems are provisioned based on the corresponding virtual system template for the first configuration entry. The method additionally includes storing the provisioned virtual systems in a resource pool and processing a provisioning request utilizing a pre-provisioned virtual system stored in the resource pool.