Patents Examined by Edward Dudek, Jr.
  • Moving blocks of data between main memory and storage class memory
    Patent number: 9418006
    Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: August 16, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peter D. Driever, Steven G. Glassen, Kenneth J. Oakes, Peter G. Sutton, Harry M. Yudenfriend
  • Cache replacement policy methods and systems
    Patent number: 9418019
    Abstract: An embodiment includes a system, comprising: a cache configured to store a plurality of cache lines, each cache line associated with a priority state from among N priority states; and a controller coupled to the cache and configured to: search the cache lines for a cache line with a lowest priority state of the priority states to use as a victim cache line; if the cache line with the lowest priority state is not found, reduce the priority state of at least one of the cache lines; and select a random cache line of the cache lines as the victim cache line if, after performing each of the searching of the cache lines and the reducing of the priority state of at least one cache line K times, the cache line with the lowest priority state is not found. N is an integer greater than or equal to 3; and K is an integer greater than or equal to 1 and less than or equal to N?2.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: August 16, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kevin Lepak, Tarun Nakra, Khang Nguyen, Murali Chinnakonda, Edwin Silvera
  • System and method for an accelerator cache based on memory availability and usage
    Patent number: 9411736
    Abstract: The storage processor of a data storage system such as a storage array automatically configures one or more accelerator caches (“AC”) upon detecting the presence of one or more solid-state storage devices (e.g., SSD drives) installed in the data storage system, such as when a storage device is plugged into a designated slot of the data storage system, without requiring any user configuration of the AC or specification by the user of the type(s) of data to be cached in the AC. The AC therefore provides a zero configuration cache that can be used to cache any of various types of data in the data storage system. The AC cache can be used in any of a wide variety of data storage systems including, without limitation, file servers, storage arrays, computers, etc. Multiple ACs may be created to cache different types of data.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: August 9, 2016
    Assignee: Drobo, Inc.
    Inventors: Jason P. O'Broin, Rodney G. Harrison, Terence M. Rokop
  • Clearing blocks of storage class memory
    Patent number: 9411737
    Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: August 9, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peter D. Driever, Steven G. Glassen, Kenneth J. Oakes, Peter G. Sutton, Peter K. Szwed, Harry M. Yudenfriend
  • Secure reservation mode for logical unit numbers and persistent reservations
    Patent number: 9405469
    Abstract: A mapping system and method that enables a secure reservation mode for a plurality of logical unit numbers of a storage system, generates a plurality of secret reservation keys, and instructs a distributed client to utilize at least one of the secret reservation keys to register with the storage system and to issue secure persistent reserves to the plurality of logical unit numbers.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: August 2, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Susan K. Candelaria, Scott B. Compton, Jared M. Minch, Richard A. Ripberger, Harry M. Yudenfriend
  • System and method of optimization of in-memory data grid placement
    Patent number: 9405589
    Abstract: A method, system, and program product for optimizing distribution and availability of data partitions is disclosed. Placement logic is run for data partition distribution which optimizes a configuration of a memory data grid. A performance impact of adding new members to the memory data grid is provided. Replication of data partitions in the memory data grid is minimized. Optimum data partition distribution in the memory data grid is determined.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: August 2, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nitin Gaur, Kulvir S. Bhogal, Christopher D. Johnson, Todd E. Kaplinger, Douglas C. Berg
  • Priority command queues for low latency solid state drives
    Patent number: 9400615
    Abstract: A method, apparatus, and system of a priority command queues for low latency solid state drives are disclosed. In one embodiment, a system of a storage system includes a command sorter to determine a target storage device for at least one of a solid state drive (SSD) command and a hard disk drive (HDD) command and to place the command in a SSD ready queue if the SSD command is targeted to a SSD storage device of the storage system and to place the HDD command to a HDD ready queue if the HDD command is targeted to an HDD storage device of the storage system, a SSD ready queue to queue the SSD command targeted to the SSD storage device, and a HDD ready queue to queue the HDD command targeted to the HDD storage device.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: July 26, 2016
    Assignee: NETAPP, INC.
    Inventors: Brian McKean, Kevin Kidney, Jeremy Pinson
  • Storage device, protection method, and electronic apparatus
    Patent number: 9396137
    Abstract: According to one embodiment, a storage device includes, when power is supplied to a storage unit, counting of an elapsed time is started. If a command is input from a host device, and the elapsed time from input of a previous command to input of a current command is calculated based on time information clocked by the host device and on a counter value counted until the corresponding command is input. Matching of the time information is determined based on a temporal relation between the adding result of adding the calculated elapsed time to the time information included in the previous command and the time information included in the current command. When the mismatching is determined, data in the storage unit is invalidated.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: July 19, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Nagai, Mitsunori Tadokoro, Teruji Yamakawa, Kazuo Nakashima
  • Online iteration resource allocation for large sector format drive
    Patent number: 9384778
    Abstract: Systems and methods for resource allocation for a large sector format processing may include, but are not limited to, operations for: determining non-convergence of a magnetic disc sub-sector of a first magnetic disc sector within a processing time frame allocated to the magnetic disc sub-sector; determining a convergence of a second magnetic disc sector occurring in less time than a processing time frame allocated to the second magnetic disc sector; and processing the magnetic disc sub-sector during a portion of the processing time frame allocated to the second magnetic disc sector remaining after processing of the second magnetic disc sector.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: July 5, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte Ltd.
    Inventors: Shu Li, Fan Zhang, Jun Xiao
  • Techniques for performing data migration
    Patent number: 9383940
    Abstract: Described are techniques for performing data migration for a source logical volume and a target. The target is configured as storage for another mirror of the source logical volume prior to copying data from the source logical volume to the target, and if the target is configured storage of another logical volume of the data storage system, the configured storage is remapped as storage for another mirror of the source logical volume prior to copying data from the source logical volume to the target. One or more invalid bits are set indicating that the target does not contain a valid copy of data from the source logical volume. Data is copied from the first mirror of the source logical volume to the target. Invalid bits are cleared as data portions of the first mirror of the source logical volume are copied to the target.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: July 5, 2016
    Assignee: EMC Corporation
    Inventors: Stephen Richard Ives, John F. Madden, Jr., Michael Dudnik, Hagit Brit-Artzi, Roii Raz, Hui Wang, Gabi Hershkovitz, Qun Fan, Ofer Michael
  • Secure reservation mode for logical unit numbers and persistent reservations
    Patent number: 9378154
    Abstract: A mapping system and method that enables a secure reservation mode for a plurality of logical unit numbers of a storage system, generates a plurality of secret reservation keys, and instructs a distributed client to utilize at least one of the secret reservation keys to register with the storage system and to issue secure persistent reserves to the plurality of logical unit numbers.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: June 28, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Susan K. Candelaria, Scott B. Compton, Jared M. Minch, Richard A. Ripberger, Harry M. Yudenfriend
  • Memory controllers, systems, and methods supporting multiple request modes
    Patent number: 9378787
    Abstract: A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: June 28, 2016
    Assignee: Rambus Inc.
    Inventors: Richard E. Perego, Frederick A. Ware
  • Tiered-storage design
    Patent number: 9372636
    Abstract: A method, computer program product, and computing system for defining a storage pool for a storage system being designed that includes a plurality of storage tiers. Each storage tier has a different level of performance. A first workload is defined for the storage system, wherein the first workload includes: a first target skew factor, a first capacity requirement, and a first IOPS requirement. A first density function is generated based, at least in part, upon the first target skew factor. The first workload is applied to the storage pool, thus defining a first allocated workload. A distribution of the first IOPS requirement amongst the plurality of storage tiers included within the storage pool is determined based, at least in part, upon the first allocated workload and the first density function.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: June 21, 2016
    Assignee: EMC Corporation
    Inventors: Dave Zeryck, Denis Vilfort
  • Configure storage class memory command
    Patent number: 9372640
    Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: June 21, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peter D. Driever, Charles W. Gainey, Jr., Steven G. Glassen, Thomas B. Mathias, Kenneth J. Oakes, Peter G. Sutton, Peter K. Szwed, Elpida Tzortzatos, Harry M. Yudenfriend
  • System and method of a shared memory hash table with notifications
    Patent number: 9367251
    Abstract: A method and apparatus of a device that includes a shared memory hash table that notifies one or more readers of changes to the shared memory hash table is described. In an exemplary embodiment, a device modifies a value in the shared memory hash table, where the value has a corresponding key. The device further stores a notification in a notification queue that indicates the value has changed. In addition, the device invalidates a previous entry in the notification queue that indicates the value has been modified. The device signals to the reader that a notification is ready to be processed.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: June 14, 2016
    Assignee: Arista Networks, Inc.
    Inventors: Hugh W. Holbrook, Duncan Stuart Ritchie, Sebastian Sapa, Simon Francis Capper
  • Method and apparatus for shared line unified cache
    Patent number: 9361233
    Abstract: An apparatus and method for implementing a shared unified cache. For example, one embodiment of a processor comprises: a plurality of processor cores grouped into modules, wherein each module has at least two processor cores grouped therein; a plurality of level 1 (L1) caches, each L1 cache directly accessible by one of the processor cores; a level 2 (L2) cache associated with each module, the L2 cache directly accessible by each of the processor cores associated with its respective module; a shared unified cache to store data and/or instructions for each of the processor cores in each of the modules; and a cache management module to manage the cache lines in the shared unified cache using a first cache line eviction policy favoring cache lines which are shared across two or more modules and which are accessed relatively more frequently from the modules.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: June 7, 2016
    Assignee: INTEL CORPORATION
    Inventors: Liang-Min Wang, John M. Morgan, Namakkal N. Venkatesan
  • Memory centric computing
    Patent number: 9348539
    Abstract: A hybrid memory system. This system can include a processor coupled to a hybrid memory buffer (HMB) that is coupled to a plurality of DRAM and a plurality of Flash memory modules. The HMB module can include a Memory Storage Controller (MSC) module and a Near-Memory-Processing (NMP) module coupled by a SerDes (Serializer/Deserializer) interface. This system can utilize a hybrid (mixed-memory type) memory system architecture suitable for supporting low-latency DRAM devices and low-cost NAND flash devices within the same memory sub-system for an industry-standard computer system.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: May 24, 2016
    Assignee: INPHI CORPORATION
    Inventors: Nirmal Raj Saxena, David Wang, Christopher Haywood, Eric McDonald, Chao Xu
  • Lifetime extension of non-volatile semiconductor memory for data storage device
    Patent number: 9348520
    Abstract: Lifetime extension of a non-volatile semiconductor memory (NVSM) for a data storage device (DSD) includes determining a write amplification factor based on an amount of data previously written to the NVSM and at least one of an amount of data previously requested to be written to the DSD, and an amount of data previously requested to be written to the NVSM. At least a portion of the amount of data to be written to the NVSM is directed or redirected to the disk based on the determined write amplification factor.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: May 24, 2016
    Assignee: Western Digital Technologies, Inc.
    Inventors: Lu Ding, Choo-Bhin Ong, Chandra M. Guda, Michael C. Kutas
  • Method and system for full resolution real-time data logging
    Patent number: 9330014
    Abstract: A method and data-logging system are provided. The system includes a map-ahead thread configured to acquire blocks of private memory for storing data to be logged, the blocks of private memory being twice as large as the file page size, a master thread configured to write data to the blocks of private memory, in real-time and in full resolution, the data acquired during operation of a machine generating the data and written to the blocks of private memory in real-time, the machine including a controller including a processor communicatively coupled to a memory having processor instructions therein, and a write-behind thread configured to acquire pages of memory that are mapped to pages in a file, copy the data from the blocks of private memory to the acquired file-mapped blocks of memory.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: May 3, 2016
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Benno Orschel, Mike Wolfram
  • Rapid creation and reconfiguration of virtual machines on hosts
    Patent number: 9329889
    Abstract: A rapid virtual machine (VM) cloning technique is provided that creates cloned VMs on hosts from multiple source VMs, rather than a single source VM that may otherwise be a bottleneck. The described technique selects particular hosts, disposed in particular racks, on which to create VM clones in a dynamic manner that reduces total deployment time for the plurality of VMs. A rapid VM reconfiguration technique is also provided that reduces the time spent reconfiguring the provisioned VMs for use in a distributed computing application.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: May 3, 2016
    Assignee: VMware, Inc.
    Inventors: Yonghua Lin, Qiuhui Li, Junping Du, Xiaoding Bian, Guang Lu