Abstract: A host interface controller with improved boot up efficiency, which uses a buffer mode setting register to set the operation mode of a first and a second buffer set provided within the host interface controller. When a cache memory of a central processing unit (CPU) at the host side has not started up, the first and second buffer sets operate in a cache memory mode to respond to read requests that the CPU repeatedly issues for data of specific addresses of the storage device. When the cache memory has started up, the first buffer set and the second buffer set operate in a ping-pong buffer mode to respond to read requests that the CPU issues for data of sequential addresses of the storage device.

Abstract: A method for enabling applications to compress and un-compress selected objects based on defined rules is provided. The method may include generating un-compressed objects and proxy objects, and storing the generated un-compressed objects on an un-compressed objects storage. The method may include receiving defined rules. The method may include compressing the stored un-compressed objects based on the defined rules, and storing the generated compressed objects on a compressed objects storage. The method may include receiving requests to invoke methods. The method may include in response to a determination that the received requests are to invoke methods associated with the un-compressed objects, retrieving the stored un-compressed objects. The method may include in response to a determination that the received requests are to invoke methods associated with the stored compressed objects, retrieving the compressed objects. The method may include restoring the retrieved compressed objects.

Abstract: A data processing device includes a hash table management module that sequentially steps through linear address space of the hash table to identify hash chain in sequential address order. Each identified hash chain is evaluated, before identifying a next hash chain, to remove any entries marked for deletion.

Abstract: A method of processing input/output (I/O) in a storage device includes adjusting a read anticipation time based on a change of a resource management status related to operations of the storage device and performing an I/O processing operation at the storage device based on the adjusted read anticipation time. The I/O processing operation is performed to postpone an operation regarding a program command and perform a read command at higher priority than a write command at the storage device in a period from completion of a read operation at the storage device until the read anticipation time has elapsed.

Abstract: A control unit calculates the expected number of access operations to each recorded data set, and selects one or more recorded data sets as recorded data sets to be relocated, based on the expected number of access operations. The control unit calculates the expected number of access operations to each recorded data set, based on a calculation period and the number of access operations per unit time. The calculation period differs from one recorded data set to another, depending on the next update timing. If the next update timing is earlier than the next relocation timing, the calculation period is a period from the current relocation timing to the next update timing. On the other hand, if the next update timing is later than the next relocation timing, the calculation period is a period from the current relocation timing to the next relocation timing.

Abstract: Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.

Abstract: One embodiment sets forth a technique for time-multiplexed communication for transmitting command and address information between a controller and a multi-port memory device over a single connection. Command and address information for each port of the multi-port memory device is time-multiplexed within the controller to produce a single stream of commands and addresses for different memory requests. The single stream of commands and addresses is transmitted by the controller to the multi-port memory device where the single stream is demultiplexed to generate separate streams of commands and addresses for each port of the multi-port memory device.

Abstract: Techniques are described for formally expressing whether sequences of operations performed on block storage devices are sequential or random. In embodiments, determinations of whether these sequences of operations are sequential or random may be used to predict latencies involved with running particular workloads, and to predict representative workloads for particular latencies.

Abstract: In addition to caching I/O operations at a host, at least some data management can migrate to the host. With host side caching, data sharing or deduplication can be implemented with the cached writes before those writes are supplied to front end storage elements. When a host cache flush to distributed storage trigger is detected, the host deduplicates the cached writes. The host aggregates data based on the deduplication into a “change set file” (i.e., a file that includes the aggregation of unique data from the cached writes). The host supplies the change set file to the distributed storage system. The host then sends commands to the distributed storage system. Each of the commands identifies a part of the change set file to be used for a target of the cached writes.

Abstract: Provided is a refresh control device including: an arbitration operating unit configured to arbitrate (i) a memory access request for accessing a volatile memory that requires a refresh operation for holding data and (ii) a refresh trigger for requesting execution of the refresh operation; and a trigger generating unit configured to generate refresh triggers in a non-constant cycle to satisfy refresh-rate requirements defining the number of refresh operations necessary to be executed per predetermined period for the volatile memory to hold the data.

Abstract: A method, system, and computer program product for intercepting IO to a virtual machine file system by a storage based splitter, replicating, via a replication appliance, the IO to a replica of the image; the replica of the image containing a replica of the virtual machine file system, and periodically mounting the replica of the virtual machine file system to create entries for a database tracking information about the virtual machines running in the hypervisor.

Abstract: An address translation capability in which information is obtained from an address translation structure to be used to translate a first address to a second address, the first address being of a first address type and the second address being of a second address type. The address translation structure includes a first set of information to translate the first address to one address of the second address type and a second set of information to translate the first address to another address of the second address type. To obtain the information, the first set of information or the second set of information is selected as the information to be used to translate the first address to the second address, based on an attribute of the first address.

Abstract: An address translation capability in which information is obtained from an address translation structure to be used to translate a first address to a second address, the first address being of a first address type and the second address being of a second address type. The address translation structure includes a first set of information to translate the first address to one address of the second address type and a second set of information to translate the first address to another address of the second address type. To obtain the information, the first set of information or the second set of information is selected as the information to be used to translate the first address to the second address, based on an attribute of the first address.

Abstract: Provided is a storage system including: a storage medium including a plurality of physical storage areas having an upper limit number of rewrites, and a medium controller that controls I/O (input/output) of data to/from the plurality of physical storage areas; and a storage controller connected to the storage medium, wherein when any of the physical storage areas is not allocated to a write destination logical storage area among a plurality of logical storage areas, the medium controller allocates a vacant physical storage area among the plurality of physical storage areas to the write destination logical storage area and writes write target data to the allocated vacant physical storage area, and the plurality of logical storage areas includes an available logical area group determined based on a relationship between an available capacity of a logical storage capacity and a rewrite frequency of the plurality of physical storage areas.

Abstract: In one embodiment, a system includes a back-end storage device, a cache storage device, and a processor and logic integrated with and/or executable by the processor. The logic is configured to store data to the cache storage device using fine block descriptors (FBDs) configured for fine-grained mapping of variable-size cache allocations. The logic is also configured to store data to the back-end storage device using cache block descriptors (CBDs) configured for coarse-grained mapping of large blocks of data. At least some FBDs are smaller in size than any of the CBDs, and all FBDs are equal to or smaller in size than any of the CBDs.

Abstract: A method for data storage includes defining an end-to-end mapping between data bits to be stored in a memory device that includes multiple memory cells and predefined programming levels. The data bits are mapped into mapped bits, so that the number of the mapped bits is smaller than the number of the data bits. The data bits are stored in the memory device by programming the mapped bits in the memory cells using a programming scheme that guarantees the end-to-end mapping. After storing the data bits, the data bits are read from the memory device in accordance with the end-to-end mapping.

Abstract: A host interface controller with improved boot up efficiency, which uses a buffer mode setting register to set the operation mode of a first and a second buffer set provided within the host interface controller. When a cache memory of a central processing unit (CPU) at the host side has not started up, the first and second buffer sets operate in a cache memory mode to respond to read requests that the CPU repeatedly issues for data of specific addresses of the storage device. When the cache memory has started up, the first buffer set and the second buffer set operate in a ping-pong buffer mode to respond to read requests that the CPU issues for data of sequential addresses of the storage device.

Abstract: Conventional storage filers utilize a data reading process that requires client read request messages to be suspended in the operating system while the data is retrieved from the physical storage system. Then, once the operating system retrieves the data from the physical storage system, the operating system must restart the suspended read message in order to forward the retrieved data to the client. Accordingly, the inventors have developed a system and method that allows the physical storage system's server to send the data directly to the client rather than routing back through the operating system.

Abstract: A processor implementing techniques to supporting fault information delivery is disclosed. In one embodiment, the processor includes a memory controller unit to access an enclave page cache (EPC) and a processor core coupled to the memory controller unit. The processor core to detect a fault associated with accessing the EPC and generate an error code associated with the fault. The error code reflects an EPC-related fault cause. The processor core is further to encode the error code into a data structure associated with the processor core. The data structure is for monitoring a hardware state related to the processor core.

Abstract: In accordance with the present disclosure, a system and method for performing a system memory save in tiered or cached storage during transition to a decreased power state is disclosed. As disclosed herein, the system incorporating aspects of the present invention may include a solid-state drive, volatile memory, and at least one alternate storage media. Upon transition to a decreased power state, at least some of the data in the solid-state drive may be transferred to the at least one alternate storage media. After the SSD data is transferred, data stored in volatile system memory, such as a system context, may be transferred to the SSD memory. With the system context saved in SSD memory, power to the volatile system memory may be turned off.