Patents Examined by Edward Dudek, Jr.
  • Patent number: 9727247
    Abstract: In order to enable an improvement in the access performance of a storage, a storage includes first and second storage devices respectively including first and second storage units to and from each of which data can be written and read, the speed of the first storage device is higher than or equal to that of the second storage device, the first storage device further includes a first storage area for storing management information for access control and management of the second storage unit, the second storage device further includes a second storage area for storing management information for access control and management of the second storage unit, and the storage includes an access control unit which retrieves the management information relating to the second storage unit and used for access to the second storage unit from the first storage area of the first storage device, and retrieves the management information relating to the second storage unit from the second storage area of the second storage device
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: August 8, 2017
    Assignee: NEC CORPORATION
    Inventor: Shugo Ogawa
  • Patent number: 9715347
    Abstract: Techniques for managing the migration of data from one virtual machine to another using volume snapshotting and sub-file cloning are described. According to exemplary embodiments, data including a header and content is stored on a storage volume associated with a first virtual machine. The header is converted to be compatible with a second virtual machine, and the storage volume is snapshotted to provide a read-only representation of the storage volume at the time that the snapshot was created. New data is created using the converted header and a pointer to the location of the data inside the volume snapshot. Using the exemplary techniques described herein, data can be migrated from one virtual machine to another in constant time, and data access is more robust because the pointer refers to the volume snapshot.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: July 25, 2017
    Assignee: NETAPP, INC.
    Inventors: Sungwook Ryu, Joshua Flank, Pradeep Thirunavukkarasu
  • Patent number: 9715458
    Abstract: A computer system has physical processors supporting virtual addressing. Virtual processors represent multiple execution threads, and logical state of all threads of a virtual processor is stored in a state descriptor field in main memory when the virtual processor is removed from one of the physical processors. Each thread has assigned a thread identifier, which is unique in the respective virtual processor only, and each virtual processor has assigned a unique state descriptor identifier. Address translations for the threads of the multiple virtual processors under their respective thread identifier and state descriptor identifier are stored, and a sequence number is generated when an entry in the translation lookaside buffer is created. The sequence number is stored together with a respective thread identifier, state descriptor identifier, and a valid bit in a respective translation lookaside buffer entry.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: July 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas Koehler, Frank Lehnert
  • Patent number: 9715443
    Abstract: A method and apparatus of memory management are disclosed. Pooling of at least one memory to generate a memory pool, dividing the memory pool to generate at least one memory space, and allocating a respective memory space to a respective CPU in a one-to-one correspondence manner are performed. Further, the respective memory space allocated to the respective CPU is set as a pinned memory of the respective CPU. Additionally, setting unallocated memory space as a shared memory pool, obtaining a memory value that represents usage of the respective memory space by the respective CPU during operation, and determining if the memory value exceeds a preset threshold range are performed. Selecting, if the memory value exceeds the preset threshold range, additional memory space from the memory pool to allocate to the respective CPU or reallocating at least a portion of the respective memory space allocated to the CPU are performed.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: July 25, 2017
    Assignee: Alibaba Group Holding Limited
    Inventors: Gongbiao Niu, Zhen Huang
  • Patent number: 9710197
    Abstract: According to one embodiment, A storage device includes a magnetic disk, a head, and a control unit. The magnetic disk includes a plurality of physical sectors having a first length. A logical block having a second length shorter than the first length, and a redundant area having a length of the difference between the first length and the second length are assigned for the physical sectors. The head reads the data from the physical sector of the magnetic disk. The control unit controls to change the second length of the logical block while maintaining the first length of the physical sector in response to reception of a change request for changing the second length of the logical block from a host.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: July 18, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Michihiko Umeda, Hidekazu Masuyama, Nobuhiro Sugawara, Yasuyuki Nagashima, Seiji Toda, Takato Kuji
  • Patent number: 9710183
    Abstract: A primary physical storage device has effectively limitless apparent free space. Responsive to receiving a request to dynamically allocate an amount of desired free space on the primary device to store new data on the primary device, and responsive to determining that an amount of actual free space on the primary device is insufficient to permit such allocation, existing data stored on the primary device is moved to a secondary storage device. The first existing data appears to still be stored on the primary device. Responsive to receiving a request to retrieve existing data from the primary device, and to determining that the existing data has been moved to the secondary device, the existing data is moved back to the primary device. The existing data was originally stored on the primary device, and is currently stored on the primary device or has been moved to the secondary device.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: July 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Dustin A. Helak, Marc A. Martin, Jason Webster
  • Patent number: 9703701
    Abstract: A group address range is mapped to a memory address range of a nonvolatile memory. A first memory address of the memory address range is to be copied to a volatile memory if the first memory address is mapped to the group address range and a write access is requested for the first memory address. The group address range is transferred from a first node to a second node in response to a synch command. The copied address is to be written the NVM after the group address range is transferred.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: July 11, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Douglas L Voigt
  • Patent number: 9696929
    Abstract: When a power-saving period registered in device management information is reached, a processor of a storage control apparatus sets an operation mode of the corresponding storage device to a power-saving mode. In addition, the processor deletes identification information of data stored in a storage device whose power-saving period is registered in the device management information, from data management information in which identification information of data that could be copied to a cache from at least one access-destination storage device asynchronously with access by the host apparatus is registered.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: July 4, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Tomohiko Muroyama, Tadashi Matsumura, Noriyuki Yasu, Motoki Sotani
  • Patent number: 9690505
    Abstract: A table may include first and second row addresses that are adjacent an activated row address. A first counter of the first row address may be incremented if the activated row address is not included in the table. A second counter of the second row address may also be incremented if the activated row address is not included in the table. The first row address may be refreshed if the first counter exceeds a counter threshold. The second row address may be refreshed if the second counter exceeds the counter threshold.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: June 27, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Melvin K. Benedict
  • Patent number: 9684608
    Abstract: Embodiments of an invention for maintaining a secure processing environment across power cycles are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction to evict a root version array page entry from a secure cache. The execution unit is to execute the instruction. Execution of the instruction includes generating a blob to contain information to maintain a secure processing environment across a power cycle and storing the blob in a non-volatile memory.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: June 20, 2017
    Assignee: Intel Corporation
    Inventors: Francis McKeen, Vincent Scarlata, Carlos Rozas, Ittai Anati, Vedvyas Shanbhogue
  • Patent number: 9684467
    Abstract: Methods, systems, and programs are presented for managing a storage device memory. One method includes an operation for receiving a request to pin a volume stored in the storage device. The device includes disk storage and a solid state drive (SSD) cache, where pinned volumes in the storage device have all active volume data in the SSD cache. Further, the method includes an operation for determining the maximum amount of pinnable space in the SSD cache, the maximum amount of pinnable space being calculated based on the sizes of the disk storage and the SSD cache. Further, the method includes operations for determining the available pinning space, which is the maximum amount of pinnable space minus the current amount of pinned data in the SSD cache, and for granting the request to pin the volume when the available pinning space is greater than or equal to a size of the volume.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: June 20, 2017
    Assignee: Nimble Storage, Inc.
    Inventors: Senthil Kumar Ramamoorthy, Pradeep Shetty, Mukul Kumar Singh, Hy Vu
  • Patent number: 9684462
    Abstract: Method and apparatus for storing records in non-uniform access memory. In various embodiments, the placement of records is localized in one or more regions of the memory. This can be accomplished utilizing different ordered lists of hash functions to preferentially map records to different regions of the memory to achieve one or more performance characteristics or to account for differences in the underlying memory technologies. For example, one ordered list of hash functions may localize the data for more rapid access. Another list of hash functions may localize the data that is expected to have a relatively short lifetime. Localizing such data may significantly improve the erasure performance and/or memory lifetime, e.g., by concentrating the obsolete data elements in one location. Thus, the two or more lists of ordered hash functions may improve one or more of access latency, memory lifetime, and/or operation rate.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: June 20, 2017
    Assignee: SimpliVity Corporation
    Inventors: Arthur J. Beaverson, Paul Bowden, Sowmya Manjanatha, Jinsong Huang
  • Patent number: 9678870
    Abstract: A diagnostic apparatus comprises a diagnostic data buffer constituting a volatile memory, and a non-volatile memory capable of receiving data from the buffer. A data buffer controller is also provided and is operably coupled to the buffer and has an event alert input and a data channel monitoring input for receiving diagnostic data. The buffer receives, when the state of a buffer status memory indicates that the buffer is in an unprotected state, at least part of the diagnostic data received by the controller via the data channel monitoring input to the buffer and the controller sets the state of the buffer status memory to indicate the protected state in response to receipt of an event alert received via the event alert input. A controller monitors the buffer status memory and copies a portion of the buffer to the non-volatile memory in response to the buffer status memory being set to be indicative of the protected state.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: June 13, 2017
    Assignee: NXP USA, Inc.
    Inventors: Clemens Roettgermann, Dirk Moeller
  • Patent number: 9672919
    Abstract: A method includes, in a memory including analog memory cells, storing first data in a group of the memory cells using a first type of storage command that writes respective analog values to the memory cells in the group. Second data is stored in the memory cells in the group, in addition to the first data, using a second type of storage command that modifies the respective analog values of the memory cells in the group. Upon detecting imminent interruption of electrical power to the memory during storage of the second data, a switch is made to perform an alternative storage operation that is faster than the second type of storage command and protects at least the first data from the interruption.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: June 6, 2017
    Assignee: Apple Inc.
    Inventors: Avraham Poza Meir, Eyal Gurgi, Shai Ojalvo
  • Patent number: 9665282
    Abstract: Various embodiments for storage initialization and data destage in a computing storage environment are provided. At least a portion of data on a storage device is initialized using a background process, while one of simultaneously and subsequently destaging the at least the portion of the data to the storage device using a foreground process is performed. A persistent metadata bitmap, adapted to indicate whether the at least the portion of the data has been initialized, is staged to cache, the cache operable in the computing storage environment. The background process maintains a volatile bitmap indicating a status of the initialization of the at least the portion of the data in direct correspondence to the metadata bitmap. As the background process initializes the at least the portion of the data, an applicable bit on the persistent metadata bitmap is cleared and a corresponding bit is set on the volatile bitmap.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: May 30, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ellen J. Grusy, Matthew J. Kalos, Kurt A. Lovrien, Matthew Sanchez
  • Patent number: 9665487
    Abstract: An application is used, by a processor, to provide directives to a tiered data object storage environment for manipulating and managing stored data objects by using an existing policy developed by a history of directives to intelligently estimate which of the data objects are to be migrated between a higher storage tier and a lower storage tier and at what appropriate time, while refraining from migrating data objects with a pending management operation.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: May 30, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert B. Basham, Joseph W. Dain, Matthew J. Fairhurst
  • Patent number: 9652385
    Abstract: An apparatus and method are provided for handling atomic update operations. The apparatus has a cache storage to store data for access by processing circuitry, the cache storage having a plurality of cache lines. Atomic update handling circuitry is used to handle performance of an atomic update operation in respect of data at a specified address. When data at the specified address is determined to be stored within a cache line of the cache storage, the atomic update handling circuitry performs the atomic update operation on the data from that cache line. Hazard detection circuitry is used to trigger deferral of performance of the atomic update operation upon detecting that a linefill operation for the cache storage is pending that will cause a chosen cache line to be populated with data that includes data at the specified address. The linefill operation causes the apparatus to receive a sequence of data portions that collectively form the data for storing in the chosen cache line.
    Type: Grant
    Filed: November 27, 2015
    Date of Patent: May 16, 2017
    Assignee: ARM Limited
    Inventors: Gregory Andrew Chadwick, Adnan Khan
  • Patent number: 9652164
    Abstract: Mass storage devices and methods of operating thereof adapted for use with a host and for storing data thereof includes at least one non-volatile memory for storing the data, at least one volatile memory, a memory controller configured for reading and writing the data and metadata to and from the non-volatile memory and the volatile memory, and an auxiliary power supply, wherein the memory controller locates the data on the non-volatile memory with the metadata. When processing a write command that requires all data to be written to the non-volatile memory before confirmation is returned to the host computer system that the write command has succeeded, the mass storage device is configured to write the data to the non-volatile memory, write the metadata to the volatile memory, and once the both data and metadata are written, return a completion status of the write command to the host computer system.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: May 16, 2017
    Assignee: Toshiba Corporation
    Inventor: Philip David Rose
  • Patent number: 9652311
    Abstract: Embodiments of the invention provide for the optimization of utilization of non-volatile memory in message queuing. In an embodiment of the invention, a method for optimizing utilization of non-volatile memory in message queuing includes receiving a new message in a message queueing system implemented in a host computing system. The method also includes storing the new message as a master message in non-volatile memory of the host computing system. The method yet further includes subsequently receiving different messages that each share redundant information with the master message. The method even yet further includes delta encoding each of the different messages and storing the delta encoded different messages in the non-volatile memory. Finally, the method includes deleting the master message from the non-volatile memory only once each of the different messages and the master message have been acknowledged by at least one consumer subscribing to the message queuing system.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: May 16, 2017
    Assignee: International Business Machines Corporation
    Inventors: Joseph Allen, Dinakaran Joseph, Gari Singh, Meeta Yadav
  • Patent number: 9645750
    Abstract: A method including increasing spare space in a storage subsystem including a flash memory, wherein the storage subsystem includes compressed data stored in the flash memory; extending a lifetime of the storage subsystem to achieve a stored selected minimum lifetime, based at least in part as a result of the increasing spare space; identifying at least one aspect associated with the lifetime of the storage subsystem; and delaying, based at least upon one identified aspect, at least one operation that reduces the lifetime of the storage subsystem, wherein the delaying at least one operation includes delaying a command that initiates the at least one operation.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: May 9, 2017
    Assignee: Seagate Technology LLC
    Inventor: Radoslav Danilak