Patents Examined by Edward Dudek, Jr.
  • Patent number: 9792207
    Abstract: A mobile device (100) includes a processing device (140), a random access memory, RAM, (150) and an embedded mass storage device (160). A first interface (IF1) is provided between the processing device (140) and the RAM (150). The first interface (IF1) supports access of the processing device (140) to the RAM (150). The mass storage device (160) includes a controller (170) and a non-volatile flash memory (180). A second interface (IF2) is provided between the controller (170) and the flash memory (180). The second interface (IF2) supports access of the controller (170) to the flash memory (180). A third interface (IF3) is provided between the controller (170) and the processing device (140). The third interface (IF3) supports access of the controller (170) to the RAM (150).
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: October 17, 2017
    Assignees: Sony Mobile Communications Inc., Sony Corporation
    Inventor: Wladyslaw Bolanowski
  • Patent number: 9792056
    Abstract: A technique for managing system drive integrity in data storage systems is disclosed. A plurality of storage drive data structures configured to store data associated with a system drive is created, wherein each storage drive data structure includes a data structure initialization string, a unique storage system identifier, a plurality of unique system drive identifiers associated with respective system drives, and a board replacement flag. Respective data structures are stored on each of the plurality of corresponding system drives. The contents of one or more of the data structures stored on one or more of the plurality of systems drives are read via an instruction initiated by a data store system. A drive type for one or more system drives is determined based on the contents.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: October 17, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Jian Gao, Peter Puhov, Zhipeng Hu, Wei He, Shay Harel
  • Patent number: 9785582
    Abstract: A data processing architecture includes a processor which may access a memory and fetch a command recorded in the memory, transmit the fetched command to a subject configured to perform an operation corresponding to the fetched command through a network, and receive a result of performing the operation from the subject and record the result of performing the operation in the memory.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: October 10, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Chang Hyun Roh
  • Patent number: 9785548
    Abstract: A hardware-assisted mechanism may improve the performance of memory reclamation operations that employ hazard pointers. The mechanism includes hazard lookaside buffers (HLBs), each implemented in hardware and locally accessible to one or more processor cores, and two new instructions. A special store instruction may write entries to local HLBs for pointers that have been or will be dereferenced but were not yet written to a shared hazard table (which requires memory barriers). Each entry may include a hazard pointer and a table address. A special test instruction may signal each HLB to determine whether it contains a particular pointer and, if so, to return a response. If the pointer does not reside in any HLB, the memory reclamation operation may search the hazard table for the pointer. If the pointer is found in an HLB or in the hazard table, the pointed-to memory location or memory block is not reclaimed.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: October 10, 2017
    Assignee: Oracle International Corporation
    Inventors: Alex Kogan, David Dice, Maurice P. Herlihy
  • Patent number: 9778874
    Abstract: The present disclosure includes devices and methods for data deduplication. One such method includes receiving a write command, transforming data associated with the write command, determining if a transformation value of the data exists in a transformation table, and responsive to a determination that the transformation value does not exist in the transformation table, writing the data associated with the write command to a memory device.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: October 3, 2017
    Assignee: Micron Technology, Inc.
    Inventor: John C. Rudelic
  • Patent number: 9778949
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for thread waiting. One of the methods includes starting, by a first thread on a processing core, a task by starting to execute a plurality of task instructions; initiating, by the first thread, an atomic memory transaction using a transactional memory system, including: specifying, to the transactional memory system, at least a first memory address for the atomic memory transaction and temporarily ceasing the task by not proceeding to execute the task instructions; receiving, by the first thread, a signal as a consequence of a second thread accessing the first memory address specified for the atomic memory transaction; and as a consequence of receiving the signal, resuming the task, by the first thread, and continuing to execute the task instructions.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: October 3, 2017
    Assignee: Google Inc.
    Inventor: Benjamin C. Serebrin
  • Patent number: 9772778
    Abstract: A block memory device and method of transferring data to a block memory device are described. Various embodiments provide methods for transferring data to a block memory device by adaptive chunking. The data transfer method comprises receiving data in a data chunk. The data transfer method then determines that the data chunk is ready to be transferred to a block memory and transfers the data chunk to the block memory. The transfer occurs over duration, repeating the above steps until the transfer is complete. The data transfer method determines that the data chunk is ready to be transferred to the block memory based on at least in part on a duration of a previous transfer.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: September 26, 2017
    Assignee: INTEL DEUTSCHLAND GMBH
    Inventor: Karsten Gjoerup
  • Patent number: 9772946
    Abstract: A method and device are provided for processing data. The method includes, after receiving data input by a data bus, according to a destination indication of the data and a valid bit field indication of the data, writing the data input by the data bus into an uplink side shared cache, polling the uplink side shared cache according to a fixed timeslot order, reading out the data in the uplink side shared cache, and outputting the data to respective corresponding channels. The method and device enable effective saving of cache resources, reduction of pressure on area and timing, and improvement of cache utilization while reliably achieving data cache and bit width conversion.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: September 26, 2017
    Assignee: ZTE Corporation
    Inventor: Xinzhuo Shi
  • Patent number: 9772787
    Abstract: A write request directed to a storage object is received at a distributed file storage service. Based on a variable stripe size selection policy, a size of a particular stripe of storage space to be allocated for the storage object is determined, which differs from the size of another stripe allocated earlier for the same storage object. Allocation of storage for the particular stripe at a particular storage device is requested, and if the allocation succeeds, the contents of the storage device are modified in accordance with the write request.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: September 26, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Matti Juhani Oikarinen, Matteo Frigo, Pradeep Vincent
  • Patent number: 9772790
    Abstract: In a method for controlling data stored in an Solid State Disk (SSD) of a data de-duplication system, a storage controller obtains stability information of a data block. The stability information comprises a reference count of the data block and a length of a period of time when the data block is stored in the SSD. The storage controller identifies a stability level of the data block according to the stability information, and sends the stability level of the data block to the SSD. The SSD moves the data block to a target block which corresponds to the stability level. Thereby, the SSD can store data blocks having a same stability level together.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: September 26, 2017
    Assignee: HUAWEI TECHNOLOGY CO., LTD.
    Inventors: Liming Wu, Bin Huang, Wan Zhao
  • Patent number: 9767030
    Abstract: Embodiments relate to saving data upon loss of power. An aspect includes sizing a write cache buffer based on parameters related to carrying out this emergency data save procedure. A computer implemented method for allocating a write cache on a storage controller includes retrieving, at run-time by a processor, one or more operating parameters of a component used in a power-loss save of the write cache. The component is selected from the group consisting of an energy storage element, a non-volatile memory, and a transfer logic. A size for the write cache on the storage controller is determined, based on the one or more operating parameters. A write cache, of the determined size, is allocated from a volatile memory coupled to the storage controller.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: September 19, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Kirk D. Lamb
  • Patent number: 9766961
    Abstract: Embodiments of the invention provide for the optimization of utilization of non-volatile memory in message queuing. In an embodiment of the invention, a method for optimizing utilization of non-volatile memory in message queuing includes receiving a new message in a message queuing system implemented in a host computing system. The method also includes storing the new message as a master message in non-volatile memory of the host computing system. The method yet further includes subsequently receiving different messages that each share redundant information with the master message. The method even yet further includes delta encoding each of the different messages and storing the delta encoded different messages in the non-volatile memory. Finally, the method includes deleting the master message from the non-volatile memory only once each of the different messages and the master message have been acknowledged by at least one consumer subscribing to the message queuing system.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: September 19, 2017
    Assignee: International Business Machines Corporation
    Inventors: Joseph Allen, Dinakaran Joseph, Gari Singh, Meeta Yadav
  • Patent number: 9767867
    Abstract: A computer system is disclosed including a printed circuit board (PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.
    Type: Grant
    Filed: September 2, 2013
    Date of Patent: September 19, 2017
    Assignee: Virident Systems, Inc.
    Inventors: Kenneth Alan Okin, George Moussa, Kumar Ganapathy, Vijay Karamcheti, Rajesh Parekh
  • Patent number: 9740415
    Abstract: A mechanism is provided for object-based storage management. A detection is made of an event being performed on or by the object. A determination is made as to whether the event meets with one or more rules in a set of rules that identify a backup or replication needing to be performed. Responsive to determining that the event meets with one or more rules in the set of rules that identify the backup or replication needing to be performed, an indication is made in a backup/replication field in metadata of the object that the backup and/or replication of the object needs to be performed. The indication in the backup/replication field in the metadata of the object causes one or more portions of the object to be backed up and/or replicated.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: August 22, 2017
    Assignee: International Business Machines Corporation
    Inventors: John T. Olson, Erik Rueger, Lance W. Russell, Christof Schmitt
  • Patent number: 9740423
    Abstract: In a computer system having a storage controller that receives a read request or a write request, a processor is configured to send to an interface device either a read-support indication, which is an indication to execute either all or a portion of read processing for read-data of the read request, or a write-support indication, which is an indication for either all or a portion of write processing for write-data of the write request. Then, the interface device, in accordance with either the read-support indication or the write-support indication, is configured to execute either all or a portion of the read processing for the read-data, or all or a portion of the write processing for the write-data, and to send to a host computer either a first response to the effect that the read processing has been completed, or a second response that the write processing has been completed.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: August 22, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Takada, Nobuhiro Yokoi, Sadahiro Sugimoto, Akira Yamamoto
  • Patent number: 9734074
    Abstract: Embodiments of the present disclosure relate to methods and apparatuses for data copy avoidance where after a data access request is received from the first storage node, what is sent by a second storage node to the first storage node is not an address of a second storage space in a second mirrored cache, but an address of a first storage space in a first cache corresponding to the second storage space. In this way, data access may be implemented directly in the first cache on the first storage node, and can reduce data communication across different storage nodes, eliminate potential system performance bottlenecks, and enhance data access performance.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: August 15, 2017
    Assignee: EMC IP Holding Company, LLC
    Inventors: Ruiyong Jia, Lei Xue, Long Zhang, Jian Gao, Peng Xie, Huibing Xiao, Zhipeng Hu
  • Patent number: 9733843
    Abstract: Embodiments of the invention provide a method, system and computer program product for dynamic caching module selection for optimized data deduplication. In an embodiment of the invention, a method for dynamic caching module selection for optimized data deduplication is provided. The method includes receiving a request to retrieve data and classifying the request. The method also includes identifying from amongst multiple different caching modules each with a different configuration a particular caching module associated with the classification of the request. Finally, the method includes deduplicating the data in the identified caching module.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: August 15, 2017
    Assignee: International Business Machines Corporation
    Inventors: Robert D. Callaway, Ioannis Papapanagiotou
  • Patent number: 9727250
    Abstract: A nonvolatile memory system includes a nonvolatile memory device and a memory controller. The nonvolatile memory device includes memory blocks each having a plurality of pages and performs a read operation on the plurality of pages on the basis of read voltages. The memory controller is configured to manage page serial numbers of some of the plurality of pages according to a program elapsed time of each of the plurality of pages. When the memory controller receives a read command and a logical address from an external device, the memory controller is configured to select at least one of the managed page serial numbers, to compare the selected at least one of the page serial numbers with a page serial number of a page corresponding to the received logical address, and to control levels of the read voltages according to a comparison result.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: August 8, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: In-Hwan Choi, ByungJune Song, Bomi Kim
  • Patent number: 9727265
    Abstract: According to one embodiment, a magnetic disk device includes a disk including a first region and a second region, a head configured to record write data to the disk, a buffer configured to store the write data up to a first capacity, and a controller configured to obtain a first processing amount based on a time to save the write data to the first region by the head and a second processing amount improved by saving the write data from the buffer to the first region, compare the first processing amount with the second processing amount, and determine whether the write data should be saved to the first region, based on a result of the comparison between the first processing amount and the second processing amount.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: August 8, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Izumi Kawakami, Hiroaki Inoue, Akio Mizuno
  • Patent number: 9727268
    Abstract: A storage block may include a first portion allocated for storage of network data associated with a storage network. The storage network may include the storage block and one or more other storage blocks. The storage block may further include a second portion allocated for storage of local data. The local data may be associated with one or more programs of a device that includes the storage block. Additionally, the storage block may include a third portion as free space of the storage block. The third portion may be maintained at approximately a target size through adjustments made to an amount of network data stored on the first portion.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: August 8, 2017
    Assignee: LYVE MINDS, INC.
    Inventors: Christian M. Kaiser, Rick Pasetto, Stephen Sewerynek