Patents Examined by Edward J Dudek
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Patent number: 11580036Abstract: An apparatus includes a processor, configured to designate a memory region in a memory, and to issue (i) memory-access commands for accessing the memory and (ii) a conditional-fence command associated with the designated memory region. Memory-Access Control Circuitry (MACC) is configured, in response to identifying the conditional-fence command, to allow execution of the memory-access commands that access addresses within the designated memory region, and to defer the execution of the memory-access commands that access addresses outside the designated memory region, until completion of all the memory-access commands that were issued before the conditional-fence command.Type: GrantFiled: July 27, 2021Date of Patent: February 14, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Ilan Pardo, Shahaf Shuler, George Elias, Nizan Atias, Adi Maymon
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Patent number: 11573725Abstract: A storage system includes an object storage server and a storage client, the object storage server obtains an object migration policy of a source bucket, where the object migration policy indicates a condition for migrating an object from the source bucket to a destination bucket in a plurality of buckets, and the object storage server migrates a first object in the source bucket to the destination bucket according to the policy migration policy when determining that the first object meets the object migration policy of the source bucket.Type: GrantFiled: June 25, 2020Date of Patent: February 7, 2023Assignee: HUAWEI CLOUD COMPUTING TECHNOLOGIES CO., LTD.Inventors: Shugang Tian, Pingchang Bai
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Patent number: 11573722Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to provide an interface to a pooled memory that is configured as a combination of local memory and remote memory, wherein the remote memory is shared between multiple compute nodes, allocate respective memory portions of the pooled memory to respective tenants, associate respective memory balloons with the respective tenants that correspond to the allocated respective memory portions, and manage the respective memory balloons based on the respective tenants and two or more memory tiers associated with the pooled memory. Other embodiments are disclosed and claimed.Type: GrantFiled: August 6, 2020Date of Patent: February 7, 2023Assignee: Intel CorporationInventors: Rasika Subramanian, Lidia Warnes, Francesc Guim Bernat, Mark A. Schmisseur, Durgesh Srivastava
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Patent number: 11573721Abstract: An approach is provided for providing optimized identification of duplicate data in a networked computing environment. An aggregate feature vector is created that is specific to an attribute of the data (e.g., a field that holds specific informational content). The aggregate feature vector has a set of dimensions that each define a specific comparison function used to test for similarity between data entries in the attribute. Each dimension in the aggregate feature vector is assigned an effectiveness, and a cost is computed for each dimension. Based on these two, a subset of dimensions is selected to form an optimized feature vector. This optimized feature vector can then be used to analyze a dataset to find matching data.Type: GrantFiled: June 24, 2021Date of Patent: February 7, 2023Assignee: International Business Machines CorporationInventors: Soma Shekar Naganna, Abhishek Seth, Neeraj Ramkrishna Singh
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Patent number: 11573741Abstract: An example method of handling, at a hypervisor on a host in a virtualized computing system, a write input/output (IO) operation to a file on a storage device having a virtual machine file system (VMFS) is described. The method includes: sorting, at the hypervisor, a scatter-gather array for the write IO operation into sets of scatter-gather elements, each of the sets including at least one scatter-gather element targeting a common file block address; resolving offsets of the sets of scatter-gather elements to identify a first scatter-gather array of transaction-dependent scatter-gather elements; generating logical transactions for the first scatter-gather array having updates to metadata of the VMFS for the file; batching the logical transactions into a physical transaction; and executing the physical transaction to commit the updates to the metadata of the VMFS on the storage device for the file.Type: GrantFiled: August 10, 2021Date of Patent: February 7, 2023Assignee: VMWARE, INC.Inventors: Prasanna Aithal, Rohan Pasalkar, Prasad Rao Jangam, Srinivasa Shantharam, Mahesh Hiregoudar, Srikanth Mahabalarao
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Patent number: 11567741Abstract: Various implementations described herein are directed to a system and methods for memory compiling. For instance, a method may include selecting source corners from a memory compiler configuration and generating a standardized set of memory instances for the selected source corners. Also, the method may include deriving a reduced set of memory instances based on the standardized set of memory instances and building a memory compiler database for a compiler space based on the standardized set of memory instances and the reduced set of memory instances.Type: GrantFiled: June 11, 2020Date of Patent: January 31, 2023Assignee: Arm LimitedInventors: Mouli Rajaram Chollangi, Sriram Thyagarajan, Hongwei Zhu, Yew Keong Chong, Pratik Ghanshambhai Satasia
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Patent number: 11567872Abstract: Methods, devices, and systems for prefetching data. First data is loaded from a first memory location. The first data in cached in a cache memory. Other data is prefetched to the cache memory based on a compression of the first data and a compression of the other data. In some implementations, the compression of the first data and the compression of the other data are determined based on metadata associated with the first data and metadata associated with the other data. In some implementations, the other data is prefetched to the cache memory based on a total of a compressed size of the first data and a compressed size of the other data being less than a threshold size. In some implementations, the other data is not prefetched to the cache memory based on the other data being uncompressed.Type: GrantFiled: July 8, 2021Date of Patent: January 31, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Pazhani Pillai, Harish Kumar Kovalam Rajendran
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Patent number: 11561705Abstract: Embodiments herein comprise a centralized NVMe-oF namespace masking and configuration repository, which may be referenced for convenience herein as a distributed configuration service (DCS). By centralizing the functionality, there is no longer a requirement that each host, network element, and subsystem have its own user interface (UI). DCS embodiments provide a single UI for a number of features, including but not limited to: (1) viewing the list of Host interfaces that are attached to the network and are registered; (2) viewing the list of Subsystem interfaces that are attached to the IP Network and are registered with the DCS; (3) viewing the storage capacity available behind each subsystem interface; and (4) allowing a user to define the Host to Subsystem interface relationships as well as define how much storage should be allocated to each Host.Type: GrantFiled: March 18, 2021Date of Patent: January 24, 2023Assignee: DELL PRODUCTS L.P.Inventors: Erik Smith, Joseph Lasalle White, Claudio Desanti
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Patent number: 11561737Abstract: According to one embodiment, an I/O command control apparatus receives authorization information. The authorization information indicates whether or not to permit an execution of an I/O command. The apparatus verifies whether the received authorization information is not tampered with, and whether the received authorization information is issued from a known authorization server. In a case where the authorization information is not tampered with, and is issued from the known server, the apparatus verifies whether or not the authorization information permits to execution of the I/O command. The apparatus permits or prohibits the execution of the I/O command or execution of a control command generated from the I/O command, based on the authorization result.Type: GrantFiled: September 10, 2021Date of Patent: January 24, 2023Assignee: Kioxia CorporationInventors: Takeshi Ishihara, Yoshihiro Ohba, Atsushi Ohba
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Patent number: 11561907Abstract: Methods and apparatuses related to access to data stored in quarantined memory media are described. Memory systems can include multiple types of memory media (e.g., volatile and/or non-volatile) and data (e.g., information included in) stored in the memory media often are subject to risks of the data being undesirably exposed to the public. For example, requests to write data in the memory media can often be made and accepted without a user's awareness, which can lead to the undesirable exposure of the data. According to embodiments of the present disclosure, a particular portion and/or location in the memory media can provide a data protection scheme such that data stored in the particular location can be refrained from being transferred out of the computing system.Type: GrantFiled: August 18, 2020Date of Patent: January 24, 2023Assignee: Micron Technology, Inc.Inventors: Radhika Viswanathan, Bhumika Chhabra, Carla L. Christensen, Zahra Hosseinimakarem
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Patent number: 11561710Abstract: The disclosure describes a programmable power management system for NAND Flash devices. In one embodiment, dedicated match logic is provided to store program counters responsible for peak power consumption of one or more NAND Flash dies. Upon detecting that a current program counter equals a stored program counter, a high current enable signal is toggled causing at least one NAND Flash die to suspend operations, thereby reducing peak power consumption of the NAND Flash device.Type: GrantFiled: January 4, 2021Date of Patent: January 24, 2023Assignee: Micron Technology, Inc.Inventors: Giuseppe Cariello, Chiara Cerafogli, Marco Domenico Tiburzi, Fulvio Rori
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Patent number: 11561718Abstract: An in-place data recovery method and system include receiving a user request to restore a virtual machine to a version corresponding to a first point in time, identifying a first snapshot of the virtual machine based on the user request, generating a second snapshot of the virtual machine, identifying a second data block in the second snapshot that includes modified data derived from data content of a first data block in the first snapshot, generating reverse incremental backup data including the first data block, and restoring the virtual machine in-place based on the reverse incremental backup data.Type: GrantFiled: March 26, 2021Date of Patent: January 24, 2023Assignee: Rubrik, Inc.Inventors: Benjamin Travis Meadowcroft, Disheng Su, Li Ding, Roman Konarev, Samir Rishi Chaudhry, Shirong Wu, Tianpei Zhang, Wei Wang
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Patent number: 11556470Abstract: A method to store a data value onto a cache of a storage hierarchy. A range of a collection of values that resides on a first tier of the hierarchy is initialized. The range is partitioned into disjointed range partitions; a first subset of which is designated as cached; a second subset is designated as uncached. The collection is partitioned into a subset of uncached data and cached data and placed into respective partitions. The range partition to which the data value belongs (i.e. the target range partition) is identified as being cached. If the cache is full all cached range partitions that do not contain the data value are designated as uncached. All values that lie in the cached range partitions designated as uncached are evicted. The data value is then inserted into the target range partition, and copied to the first tier.Type: GrantFiled: February 2, 2021Date of Patent: January 17, 2023Assignee: Kinaxis Inc.Inventor: Angela Lin
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Patent number: 11550612Abstract: A method includes receiving a memory access request comprising a first memory address and translating the first memory address to a second memory address using a first page table associated with the first virtual machine. The first page table indicates whether the memory of the first virtual machine is encrypted. The method further includes determining that the first virtual machine is nested within a second virtual machine and translating the second memory address to a third memory address using a second page table associated with the second virtual machine. The second page table indicates whether the memory of the second virtual machine is encrypted.Type: GrantFiled: June 26, 2020Date of Patent: January 10, 2023Assignee: RED HAT, INC.Inventors: Michael Tsirkin, Karen Lee Noel
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Patent number: 11526302Abstract: Memory module, computing device, and methods of reading and writing data to the memory module are disclosed. A memory module, comprises one or more dynamic random-access memories (DRAMs); and a processor configured to select a Central Processing Unit (CPU) or the Processor to communicate with the one or more DRAMs via a memory interface.Type: GrantFiled: June 19, 2020Date of Patent: December 13, 2022Assignee: AI Plus, Inc.Inventors: John Michael Smolka, Carlos Rene Weissenberg
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Patent number: 11518035Abstract: The present disclosure provides a method and an apparatus for controlling a robot, a method and an apparatus for providing service and an electronic device. The method comprises: creating, by a local robot, a file system snapshot of an application in a local operating system, and synchronizing file system data of the application to a cloud robot; running, by the cloud robot, on a cloud virtual machine pre-running the same operating system as that of the local robot, the same application as that of the local robot (101); and reversely synchronizing a running result of the application to the local robot (102).Type: GrantFiled: October 23, 2019Date of Patent: December 6, 2022Assignee: CLOUDMINDS ROBOTICS CO., LTD.Inventor: Yanfei Wen
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Patent number: 11520531Abstract: A system may include a synchronization device and an emulation chip including a processor and a memory. The processor may evaluate, during a first cycle, at least one of a set of one or more execution instructions in the memory or evaluation primitives configured to emulate a circuit, and evaluate, during a second cycle, at least one of the set of one or more execution instructions or a set of configured logic primitives. The synchronization device may interpose a gap period interposed between the first cycle and the second cycle such that during the gap period, the processor does not evaluate one or more instructions from the set of one or more execution instructions or re-evaluate primitives. The synchronization device may cause, during the first gap period, the emulation chip to perform refreshes on the memory of the emulation chip.Type: GrantFiled: December 31, 2020Date of Patent: December 6, 2022Assignee: CADENCE DESIGN SYSTEMS, INC.Inventors: Mitchell G. Poplack, Justin Schmelzer, Aruna Aluri
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Patent number: 11520718Abstract: Devices and techniques for managing hazards in a memory controller are described herein. The memory controller can receive a memory request that includes a base memory address. An index can be computed from the base memory address and a lookup, using the index, can be performed to find a lock. When the lock is found, the memory controller can store the memory request in a buffer that corresponds to the lock. In response to a signal to clear the lock, the memory controller removes the memory request from the buffer and performs the memory request.Type: GrantFiled: October 20, 2020Date of Patent: December 6, 2022Assignee: Micron Technology, Inc.Inventor: Tony Brewer
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Patent number: 11520936Abstract: A method of volume compressed header identification includes reading, by a processing device of a host, compressible data on a sector of a storage volume of a storage array. The method further includes compressing the compressible data to generate compressed data for the sector. The method further includes adding, by the processing device of the host, metadata associated with the storage volume to the compressed data. The method further includes writing the compressed data, including the added metadata, to the sector of the storage volume of the storage array.Type: GrantFiled: December 22, 2020Date of Patent: December 6, 2022Assignee: Pure Storage, Inc.Inventors: Yuval Frandzel, Kiron Vijayasankar, Alexandre Xavier Duchateau, Constantine P. Sapuntzakis
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Patent number: 11513953Abstract: The technology describes performing garbage collection while data writes are occurring, which can lead to a conflict in that a new reference to an otherwise non-referenced candidate object for garbage collection is written after the non-referenced candidate object is detected. In one example implementation, orphaned binary large objects (BLOBs) that are not referenced by a descriptor file and are beyond a certain age are detected and deleted via an object references table traversal as part of garbage collection. Before reclaiming a deleted BLOB's capacity, a background process operates to restore the deleted BLOB if a new descriptor file reference to the BLOB was written during the object references table traversal. Capacity is only reclaimed after the object references table traversal and the background processing completes, for those BLOBs that were deleted and had not been restored.Type: GrantFiled: September 8, 2020Date of Patent: November 29, 2022Assignee: EMC IP HOLDING COMPANY LLCInventors: Mikhail Danilov, Konstantin Buinov
