Abstract: A method includes allocating, via a tier allocation component, a first portion of data to a first tier memory component and writing the first portion of data to the first tier memory component in response to a first tier free list having an available entry. The method further includes evicting a second portion of data from the first tier memory component in response to the first tier free list being empty when the first portion of data is allocated to the first tier memory component and writing the first portion of data to the first tier memory component in response to evicting the second portion of data.

Abstract: A QLC based data storage device leverages a host memory buffer (HMB) to achieve QLC direct write that increases performance of the QLC data storage device and reducing or eliminating disadvantages associated with a QLC folding approach. In one example, the QLC based data storage device includes a controller configured to receive a request to write data to a non-volatile memory, determine whether the request is a sequential write operation, determine whether a HMB of the data storage device is enabled, determine whether a HMB allocation is successful for a quad-level cell direct write, and responsive to determining that the request is not the sequential write operation, the HMB of the data storage device is enabled, and the HMB allocation is successful for the quad-level cell direct write, perform a direct write operation in a quad-level cell block of the non-volatile memory.

Abstract: Systems, apparatus, and methods are disclosed comprising receiving temperature information corresponding to a write temperature of at least one of multiple pages of non-volatile memory cells of a group of non-volatile memory cells, determining a statistical measure of temperature information for the group non-volatile memory cells using the received temperature information, and storing the determined statistical measure of temperature information for the group of non-volatile memory cells. The stored determined statistical measure of temperature information can be used to optimize or improve one or more storage system operations.

Abstract: Disclosed herein are system, method, and computer program product embodiments for utilizing non-RAM memory to implement a cloud storage system. An embodiment operates by receiving a request from an on-premises computer system to securely access a cloud drive by receiving an object specific template for an object. Based on the object specific template, an object specific plugin is selected, wherein the object specific plugin is configured to provide a connection to a cloud-based repository to obtain real time data for the object. An instance of the object is generated and communicated to a cloud plugin, wherein the cloud plugin is configured to communicate to a specific cloud drive through an HTTP client and further upload the instance of the object to the specific cloud drive.

Abstract: Disclosed herein is a device equipped with flash memory, which includes memory in which at least one program is recorded and a processor for executing the program. The memory includes flash memory including a data area and a backup area, and the program divides data into two or more segments depending on whether the data can be stored in a single page and stores the same in the data area. The first segment is stored in a page along with a segment number, indicating the sequential position of the divided data, a segment offset, indicating the number of pages between the pages in which the current segment and the next segment are stored, the size of a data file name, the size of the data, and the file name. At least one additional segment may be stored in another page along with the segment number and segment offset thereof.

Abstract: A computer-implemented method includes receiving, from a user account, an operation request to perform an operation on data stored at a distributed computing environment. The operation request includes an on-premises token associated with the user account. The method also includes extracting, from the on-premises token, an access scope associated with permissions of the user account for accessing the data stored at the distributed computing environment. The method also includes translating the extracted access scope into query parameters compatible with the data stored at the distributed computing environment. The method also includes determining, using the query parameters, whether the operation request can access the data stored at the distributed computing environment. When the operation request can access the data stored at the distributed computing environment, the method includes executing the operation request.

Abstract: Provided is a storage device which communicates with a host device and configured to set a secure mode of a plurality of commands different in kind. An operating method of the storage device includes receiving a secure request indicating a protection of a first command and a protection of a second command of the plurality of commands, from the host device; setting a secure mode of the first and second commands, based on the secure request; receiving a first request indicating a request to execute the first command, from the host device; outputting a first response indicating failure of the first command to the host device, based on the first request; receiving a second request indicating a request to execute the second command, from the host device; and outputting a second response indicating failure of the second command to the host device, based on the second request.

Abstract: A memory expander includes a memory device that stores a plurality of task data. A controller controls the memory device. The controller receives metadata and a management request from an external central processing unit (CPU) through a compute express link (CXL) interface and operates in a management mode in response to the management request. In the management mode, the controller receives a read request and a first address from an accelerator through the CXL interface and transmits one of the plurality of task data to the accelerator based on the metadata in response to the read request.

Abstract: A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

Abstract: According to one embodiment, in a semiconductor device, a first chip is electrically connected to a terminal to which a signal from a host is input. The first chip is electrically connected to a second chip and to a third chip in parallel with the second chip. The first chip includes a first buffer memory and a second buffer memory. The first buffer memory corresponds to the second chip. The second buffer memory corresponds to the third chip. The second chip includes a third buffer memory. The third chip includes a fourth buffer memory. A capacity of the first buffer memory is equal to or larger than a capacity of the third buffer memory. A capacity of the second buffer memory is equal to or larger than a capacity of the fourth buffer memory.

Abstract: In described examples, a coherent memory system includes a central processing unit (CPU) and first and second level caches. The CPU is arranged to execute program instructions to manipulate data in at least a first or second secure context. Each of the first and second caches stores a secure code for indicating the at least first or second secure contexts by which data for a respective cache line is received. The first and second level caches maintain coherency in response to comparing the secure codes of respective lines of cache and executing a cache coherency operation in response.

Abstract: A storage system with a controller having a persistent memory interface to local memory is provided. The persistent memory can be used to store a logical-to-physical address table. A logical-to-physical address table manager, local to the controller or remote in a secondary controller, can be used to access the logical-to-physical address table. The manager can be configured to improve bandwidth and performance in the storage system.

Abstract: An apparatus including a CPU core and a L1 cache subsystem coupled to the CPU core. The L1 cache subsystem includes a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives an indication from the L1 controller that a cache line A is being relocated from the L1 main cache to the L1 victim cache; in response to the indication, update the shadow L1 main cache to reflect that the cache line A is no longer located in the L1 main cache; and in response to the indication, update the shadow L1 victim cache to reflect that the cache line A is located in the L1 victim cache.

Abstract: The invention discloses an aggregation optimized processing method for time-series data, characterized by comprising the following steps: writing a time-series data record into a database, forming a time-series database file, wherein the time-series database file comprises a data file and an index file, the data file comprises multiple data blocks, the index file comprises index blocks, and each index block correspond to one data block; by scanning an index file according to a start time period and a stop time period, extracting all index blocks of the time series that need to be aggregated that meet the time period conditions, and then sorting the index blocks according to the data block offset recorded in the index block; and by scanning the data file according to a data block offset order recorded in sorted index blocks, performing specified reading and calculating on each data block, and aggregating calculation results.

Abstract: An improved information management system is described herein that provides on-demand or live mount access to virtual machine data in a secondary copy format. For example, instead of restoring all of the virtual machine data in the secondary copy format to a virtual disk that is then mounted to a virtual machine, the improved information management system can, in response to request to access virtual machine data in a secondary copy format, create a virtual disk having a universal network component (UNC) path and create a virtual machine configured to access data via the UNC path. Once created and booted, the administrator or user can attempt to access the desired virtual machine data via the virtual machine.

Abstract: Aspects of the present disclosure are directed to performing varying frequency memory sub-system background scans using either or both a timer and an I/O event limit. This can be accomplished by identifying a background scan trigger event from one of multiple possible types of background scan trigger events, such as a timer expiration or reaching an event count limit. In response to the background scan trigger event, a background scan can be initiated on a memory portion. The background scan can produce results, such as CDF-based data. When a metric based on the results exceeds a background scan limit, a refresh relocation can be performed and logged. A metric can be generated based on the CDF-based data, obtained error recovery depth data, or refresh relocation event data. When the metric is above or below corresponding background scan thresholds, a background scan frequency can be adjusted.

Abstract: Systems, apparatuses, and methods related to predictive memory management are described. Error correction operations can be performed on a memory system and can include a latency associated with performing various error correction techniques on data and the health of physical addresses used to store the data can be predicted based on that latency information. In an example, a method can include determining, by a controller, latency information corresponding to one or more error correction operations performed on data received by the controller, and assigning, based on the latency information corresponding to a health of physical address locations corresponding to the data, and taking an action involving the physical address locations based, at least in part, on the information corresponding to the health of the plurality of physical address locations corresponding to the data.

Abstract: A data storage system and a global deduplication method thereof are provided. The data storage system includes multiple storage devices and one dispatch device. The dispatch device divides an original data corresponding to a data writing request into at least one data chunk. The dispatch device performs a summary calculation on one data chunk, so as to generate a representative value. The dispatch device performs a first distribution calculation on the representative value, so as to determine a destination location corresponding to the representative value. The dispatch device transmits the data chunk and the representative value to at least one destination storage device among the storage devices through a communication network according to the destination location. The at least one destination storage device checks the representative value, so as to determine whether to store the data chunk in a storage space of the at least one destination storage device.

Abstract: According to one embodiment, a controller of a memory system reorders a plurality of first write commands in an order in which writing within a first zone is executed sequentially from a next write location within the first zone. The controller transfers a plurality of write data associated with the plurality of first write commands reordered from a write buffer of a host to an internal buffer in a same order as the order of the plurality of first write commands reordered, and writes the plurality of write data transferred to the internal buffer to a first storage region managed as the first zone.

Abstract: An example memory subsystem includes a memory component and a processing device, operatively coupled to the memory component. The processing device is configured to receive a plurality of logical-to-physical (L2P) records, wherein an L2P record of the plurality of L2P records maps a logical block address to a physical address of a memory block on the memory component; determine a sequential assist value specifying a number of logical block addresses that are mapped to consecutive physical addresses sequentially following the physical address specified by the L2P record; generate a security token encoding the sequential assist value; and associate the security token with the L2P record.