Patents Examined by Edward J Dudek
  • Patent number: 11662921
    Abstract: An information handling system for managing a storage system includes storage and a storage manager. The storage is for storing a concurrency effect model for the storage system. The storage manager obtains a request for a latency prediction for the storage system; obtains media access time estimates for the storage system using a trace that specifies: a series of accesses; and responses, by the storage system, to the series of accesses; obtain concurrency estimates for the trace using the media access time estimates; obtains modifications for the media access time estimates using: the concurrency effect model; and the concurrency estimates; updates the media access time estimates using the modifications to obtain a latency prediction for the storage system; and performs an action set, based on the latency prediction, to manage operation of the storage system.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: May 30, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Vinicius Michel Gottin, Jaumir Valenca Da Silveira Junior, Renan De Campos
  • Patent number: 11662948
    Abstract: A system on a chip allows external NorFlash memory sharing by multiple master devices. The system on a chip is configured to use an external NorFlash memory and includes a plurality of master devices and NorFlash virtualising circuity. The NorFlash virtualizing circuitry is configured to suspend a program operation or an erase operation being carried out on the external NorFlash memory, permit a read operation to be carried out on the NorFlash memory and then resume the suspended program operation or erase operation. Each master device of the plurality of master devices operates as a master to independently access the external NorFlash memory.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: May 30, 2023
    Assignee: NXP USA, Inc.
    Inventors: Loic Leconte, Agathe Charligny, Regis Gaillard
  • Patent number: 11656791
    Abstract: A memory controller coupled to a memory device and a host device and configured to control access operations of the memory device includes a buffer memory, a host interface, a microprocessor and a data protection engine. The host interface is coupled to the host device and configured to write data received from the host device into the buffer memory and issue a buffer memory write complete notification after the data has been written in the buffer memory. The microprocessor is configured to trigger a data protection operation in response to the buffer memory write complete notification. The protection engine is configured to perform the data protection operation to generate corresponding protection information according to the data written in the buffer memory. The microprocessor is configured to directly trigger the data protection operation after confirming that the data has been written in the buffer memory.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: May 23, 2023
    Assignee: Silicon Motion, Inc.
    Inventor: Shen-Ting Chiu
  • Patent number: 11657185
    Abstract: Methods, systems, and devices for a memory access gate are described. A memory device may include a controller, memory dice, and a pad for receiving an externally provided control signal, such as a chip enable signal. The memory device may include a switching component for selecting the externally provided control signal or an internally generated control signal. The controller may provide the selected control signal to a memory die. The memory device may determine whether it is operating in a first mode or a second mode, and select the externally provided control signal or the internally generated control signal based on the determination. The first mode may be a diagnostic mode in some cases. The controller may include a secure register whose value may impact or control the switching. An authenticated host device may direct the controller to write the value to the secure register.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: May 23, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Giuseppe Cariello
  • Patent number: 11645204
    Abstract: An apparatus comprises a processing device configured to monitor a storage cache storing a plurality of cache pages to determine whether the storage cache reaches one or more designated conditions and to determine cache replacement scores for at least a subset of the cache pages, the cache replacement scores being determined based at least in part on input-output access types for data stored in the cache pages. The processing device is also configured to select, responsive to determining that the storage cache has reached at least one of the one or more designated conditions, at least one of the cache pages to move from the storage cache to a storage device based at least in part on the determined cache replacement scores. The processing device is further configured to move the selected at least one of the plurality of cache pages from the storage cache to the storage device.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: May 9, 2023
    Assignee: Dell Products L.P.
    Inventors: Chi Chen, Huijuan Fan, Hailan Dong
  • Patent number: 11644983
    Abstract: A storage device includes a non-volatile memory configured to store an encryption key and a data key encrypted with the encryption key, writes data using the data key, and reads the data using the data key; and a storage controller, wherein the storage controller is configured to receive a first security setting command which allows access to the data key, using a first password, generates a first key on the basis of the first password in response to the first security setting command, encrypts the encryption key with the first key to generate a first encrypted encryption key, encrypts the first key with the encryption key to generate an encrypted first key, and stores the first encrypted encryption key and the encrypted first key in the non-volatile memory.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: May 9, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myeong Jong Lee, Hyun Sook Hong, Ji Soo Kim, Seung-Jae Lee
  • Patent number: 11644975
    Abstract: Described herein are systems, methods, and software to generate user interfaces to indicate software-defined storage information in view of available hardware resources. In one example, a user interface service may obtain enclosure information associated with enclosures in a computing environment and may determine a storage overview for the plurality of enclosures based on the enclosure information. The user interface service may further determine a function for each storage device in the storage overview in relation to a software-defined storage configuration for the computing environment and generate a user interface to indicate the storage overview with the function for each storage device in the plurality of enclosures.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: May 9, 2023
    Assignee: VMware, Inc.
    Inventors: Sifan Liu, Jin Feng, Yu Wu, Denitsa Borislavova Tsvetkova, Georgi Stoyanov Georgiev, Lachezar Petkov Petkov
  • Patent number: 11640359
    Abstract: An apparatus, system, and method are disclosed for managing a non-volatile storage medium. A storage controller receives a message that identifies data that no longer needs to be retained on the non-volatile storage medium. The data may be identified using a logical identifier. The message may comprise a hint, directive, or other indication that the data has been erased and/or deleted. In response to the message, the storage controller records an indication that the contents of a physical storage location and/or physical address associated with the logical identifier do not need to be preserved on the non-volatile storage medium.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: May 2, 2023
    Assignee: Unification Technologies LLC
    Inventors: David Flynn, Jonathan Thatcher, Michael Zappe
  • Patent number: 11640266
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. The controller restricts the host to a maximum number of zones that can be in the open and active state at a time. Open zones can be switched to the closed state, and vice versa, upon a predetermined amount of time expiring. The maximum number of open zones is based on one or more amounts of time to: generate parity data, copy the parity data from the RAM2 to the RAM1, update the parity data, switch a zone from the open and active state to the closed state, and the amount of space in a temporary RAM1 buffer.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: May 2, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Liam Parker, Daniel L. Helmick, Sergey Anatolievich Gorobets
  • Patent number: 11640239
    Abstract: Cost conscious garbage collection, including: selecting one or more storage classes from among a plurality of storage classes of one or more data storage services for storing one or more data objects; determining, for the one or more data objects stored in the one or more data storage services, an estimated quantity of data eligible for garbage collection; and initiating, after determining that resources for continued storage of the one or more data objects exceed resources for performing garbage collection on the data eligible for garbage collection and based upon an expected cost savings based on storage cost savings from performing garbage collection compared against access cost expenses for performing one or more cloud-based operations to perform the garbage collection, garbage collection on the one or more data objects in the one or more data storage services.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: May 2, 2023
    Assignee: Pure Storage, Inc.
    Inventors: Dirk Meister, Subramaniam Periyagaram, Reese Robertson, Prudhvi Lokireddy
  • Patent number: 11640258
    Abstract: One example method includes powering off a replica VM, taking a snapshot of an OS disk of a source VM associated with the replica VM, taking a snapshot of an OS disk of the replica VM, generating a list of blocks that includes all blocks of the source VM OS disk that have changed since a preceding cloning or snapshot process and further includes all blocks of the replica VM OS disk that have changed since the preceding cloning or snapshot process, and performing an override of the replica VM disk by writing, to the replica VM OS disk, the respective source VM OS disk values for each block in the list of blocks.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: May 2, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Jehuda Shemer, Jawad Said, Kfir Wolfson
  • Patent number: 11640249
    Abstract: Aspects include receiving, at a portable storage device, a file from a digital device. The file is stored into an unprotected storage area on the portable storage device and a storage policy associated with the digital device is accessed by the portable storage device. It is determined, by the portable storage device, based at least in part on the portable storage policy, whether to store a copy of the file in a protected storage area on the storage device. Access to the protected storage area is restricted to authenticated users. A copy of the file is stored in the protected storage area in response to determining that a copy of the file should be stored in the protected storage area.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: May 2, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey Bisti, Philip Siconolfi, Tyler Nicole King, Robert Paquin
  • Patent number: 11630604
    Abstract: The present invention provides a method for controlling a data storage device. The data storage device includes a flash memory controller and a flash memory module. The flash memory controller has a first buffer memory and a second buffer memory. The memory module has at least a first memory portion and a second memory portion. The method includes: receiving a first data from a host device; storing the first data in the first buffer memory; transmitting the first data to the first memory portion of the flash memory module from the first buffer memory; and transmitting the first data to a host memory buffer in the host device from the first buffer memory. The first data corresponds to at least a portion of a second data to be written to the second memory portion.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: April 18, 2023
    Assignee: SILICON MOTION INC.
    Inventor: Hong-Jung Hsu
  • Patent number: 11630601
    Abstract: A method and apparatus for performing access control of a memory device with aid of a multi-phase memory-mapped queue are provided. The method includes: receiving a first host command from a host device; and in response to the first host command, utilizing a processing circuit within the controller to send a first operation command to the NV memory through a control logic circuit of the controller, and trigger a first set of secondary processing circuits within the controller to operate and interact via the multi-phase memory-mapped queue, for accessing the first data for the host device, wherein the processing circuit and the first set of secondary processing circuits share the multi-phase memory-mapped queue, and use the multi-phase memory-mapped queue as multiple chained message queues associated with multiple phases, respectively, for performing message queuing for a chained processing architecture including the processing circuit and the first set of secondary processing circuits.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: April 18, 2023
    Assignee: Silicon Motion, Inc.
    Inventors: Cheng Yi, Kaihong Wang, Sheng-I Hsu, I-Ling Tseng
  • Patent number: 11625170
    Abstract: Methods, systems, and devices for row hammer protection for a memory device are described. A memory device may identify a threshold of related row accesses (e.g., access commands or activates to a same row address or a row address space) for a memory array. In a first operation mode, the memory device may execute commands received from a host device on the memory array. The memory device may determine that a metric of the received row access commands satisfies the threshold of related row accesses. The memory device may switch the memory array from the first operation mode to a second operation mode based on satisfying the threshold. The second operation mode may restrict access to at least one row of the memory, while the first mode may be less restrictive. Additionally or alternatively, the memory device may notify the host device that the metric has satisfied the threshold.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: April 11, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Patent number: 11625337
    Abstract: Technologies disclosed herein provide cryptographic computing. An example method comprises storing, in a register, an encoded pointer to a memory location, wherein the encoded pointer comprises first context information and a slice of a memory address of the memory location, wherein the first context information includes an identification of a data key; decoding the encoded pointer to obtain the memory address of the memory location; using the memory address obtained by decoding the encoded pointer to access encrypted data at the memory location; and decrypting the encrypted data based on the data key.
    Type: Grant
    Filed: December 26, 2020
    Date of Patent: April 11, 2023
    Assignee: Intel Corporation
    Inventor: David M. Durham
  • Patent number: 11620057
    Abstract: A storage device includes: a nonvolatile memory including power loss protector (PLP) memory blocks configured to store at least one of meta data or user data for data backup; a buffer memory configured to store at least one of the meta data or the user data stored in the PLP memory blocks; a charging circuit configured to generate electric power for data backup in response to a sudden power off (SPO) occurrence, and transmit a first charging complete signal or a second charging complete signal to a processor according to a level of the electric power, and; and the processor configured to control at least one of the nonvolatile memory and the buffer memory to execute a first request from a host related to the meta data with priority in response to the first charging complete signal, and execute a second request from the host related to the meta data or the user data in response to the second charging complete signal.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: April 4, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangwoo Lim, Seongnam Kwon, Haeri Lee, Donghwan Jeong, Unseon Cho, Moonsung Choi
  • Patent number: 11620088
    Abstract: The present disclosure includes apparatuses and methods related to dual speed memory. A memory module can include a number of memory devices that coupled to a host via a number of first ports and coupled to a controller via a number of second ports. The memory module can be configured to transfer data on the first number of ports at a first clock speed and transfer data on the second number of ports at a second clock speed.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: April 4, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Frank F. Ross, Matthew A. Prather
  • Patent number: 11620066
    Abstract: A method of operating a storage device with a memory includes partitioning an entire area of a first namespace into at least one area based on a reference size. The partitioning is performed in response to a namespace creating request from a host that includes size information corresponding to the entire area of the first namespace. The method further includes partitioning a logical address space of the memory into a plurality of segments, allocating a first segment of the plurality of segments to a first area of the at least one area, and storing mapping information of the first area and the first segment. A size of the logical address space is greater than a size of a physical storage space of the memory identified by the host.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: April 4, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaewon Song, Jaesub Kim, Sejeong Jang
  • Patent number: 11614870
    Abstract: A system includes a zoned memory device allocating a zone storing a block belonging to a key-value set, and a processing device, operatively coupled with the zoned memory device, to perform operations including obtaining zone status information associated with the zone, identifying that the zone is a non-filled zone in view of the zone status information, and recovering the non-filled zone to obtain a recovered zone.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: March 28, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Pierre Labat, Nabeel Meeramohideen Mohamed, Steven Moyer