Abstract: The subject application relates to computing an authentication tag for partial transfers scheduled across multiple direct memory access (DMA) engines. Apparatuses, systems, and techniques are described for computing an authentication tag for a data transfer when the data transfer is scheduled as partial transfers across a specified number of direct memory access (DMA) engines. An orchestration circuit stores partial authentication tags, computed by the DMA engines, and corresponding adjustment exponents during one or more rounds in which the partial transfers are scheduled and processed by the specified number of DMA engines. During a last round, a combined authentication tag can be computed based on the partial authentication tags and the corresponding adjustment exponents stored by the orchestration circuit during the rounds.

Abstract: In some examples, a system detects recovery, from an unavailable state, of a communication link between a first storage system that includes a first storage volume and a second storage system that includes a second storage volume that is to be a synchronized version of the first storage volume, where while the communication link is in the unavailable state the second storage volume is in an offline state and the first storage volume is in an online state.

Abstract: A processing device in a memory system determines to send system state information associated with the memory device to a host system and identifies a subset of a plurality of event entries from a staging buffer based on one or more filtering factors, the plurality of event entries corresponding to events associated with the memory device. The processing device further sends the subset of the plurality of event entries as the system state information to the host system over a communication pipe having limited bandwidth.

Abstract: Example implementations relate to virtual persistent volumes. In an example, a manifest of a containerized application to which a virtual persistent volume is allocated is read from a container orchestrator. An application data store profile that matches information of the manifest is identified from among a plurality of application data store profiles that each include storage parameters preconfigured for a respective application type. The virtual persistent volume is modified according to the identified application data store profile.

Abstract: A vehicle memory sub-system can be switched from a normal mode to a pre-shutdown mode and initiate a media management operation before shutting down. The mode switch and/or media management operation can be performed in response to receiving a shutdown or pre-shutdown command for the vehicle. After completion of the memory management operation the vehicle and/or memory sub-system can be shutdown.

Abstract: A local media controller of a first memory device receives a first number of cycles broadcasted by a second memory device via a bus connecting the first memory device and the second memory device. The local media controller initializes a counter associated with the first memory device. Responsive to determining that the value of the counter matches the first number of cycles, the local media controller transmits a status of the first memory device via the bus. Furthermore, responsive to determining that the status is ready, the local media controller sends, to a memory sub-system controller managing the first memory device, a status of a memory region of the first memory device.

Abstract: A memory system includes a nonvolatile memory, a volatile memory, and a memory controller. The volatile memory includes a write buffer. The memory controller receives commands stored in a queue by a host device from the queue. The memory controller receives a command stored in a queue by the host device from the queue and, in a state where first data not satisfying a write unit is stored in the write buffer, when receiving a first command for writing the first data to the nonvolatile memory from the queue, simultaneously writes the first data and second data acquired from the host device or a predetermined region of the volatile memory different from the write buffer to the nonvolatile memory.

Abstract: Example implementations relate to virtual persistent volumes. In an example, a manifest of a containerized application to which a virtual persistent volume is allocated is read from a container orchestrator. An application data store profile that matches information of the manifest is identified from among a plurality of application data store profiles that each include storage parameters preconfigured for a respective application type. The virtual persistent volume is modified according to the identified application data store profile.

Abstract: Examples implementations relate to configuration of computational drives. An example computational drive includes a housing to be inserted in a drive bay of a host device, and persistent storage. The computational drive may also include a processor to respond to an insertion of the housing into the drive bay of the host device by configuring the computational drive to operate as a new node of a distributed file system, and connecting the computational drive to the distributed file system as the new node.

Abstract: Systems, apparatuses, and methods for dynamically coalescing multi-bank memory commands to improve command throughput are disclosed. A system includes a processor coupled to a memory via a memory controller. The memory also includes processing-in-memory (PIM) elements which are able to perform computations within the memory. The processor generates memory requests targeting the memory which are sent to the memory controller. The memory controller stores commands received from the processor in a queue, and the memory controller determines whether opportunities exist for coalescing multiple commands together into a single multi-bank command. After coalescing multiple commands into a single combined multi-bank command, the memory controller conveys, across the memory bus to multiple separate banks, the single multi-bank command and a multi-bank code specifying which banks are targeted. The memory banks process the command in parallel, and the PIM elements process the data next to each respective bank.

Abstract: Various examples are directed to systems and methods for managing a memory device. Processing logic may identify a set of retired blocks at the memory device that were retired during use of the memory device. The processing logic may modify a first table entry referencing the first block to indicate that the first block is not retired. The processing logic may also modify a second table entry referencing the second block to indicate that the second block is not retired. The processing logic may also recreate a logical-to-physical table entry for a first page of at the first block, the logical-to-physical table entry associating a logical address with the first page.

Abstract: An illustrative method includes a storage-aware serverless function management system monitoring one or more serverless function instances of one or more serverless functions implemented in a serverless system, the one or more serverless function instances associated with one or more components of a storage system, determining a portion of a component among the one or more components of the storage system based on the monitoring, and requesting the storage system to adjust storage of data associated with the portion of the component.

Abstract: Provided is an operating method of a memory controller which comprises receiving first decision data of M bits from a memory device, where M is a natural number; converting the M-bit first decision data into second decision data of N bits, where N is a natural number less than M; and attempting a first decoding using the second decision data.

Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.

Abstract: The present disclosure relates to a method for scheduling a computation graph on a processing in memory (PIM) enabled device comprising a memory block assembly. The method comprises allocating a first node of the computation graph on a first memory block of a first array of memory blocks in the memory block assembly and allocating a second node of the computation graph on a second memory block of a second array of memory blocks in the memory block assembly, wherein output data of the first node is used for executing the second node. The memory block assembly can be configured to support data transfer from the first memory block to the second memory block via an internal data coupling in the memory block assembly.

Abstract: A computer includes a memory and a cache holding a part of data stored in the memory in any of a plurality of data regions. In a case of replacing first data of a first data size held in the cache with second data of a second data size larger than the first data size, allocation of data regions of the cache is changed in units of the second data size by referring to a first management list that includes a plurality of first entries that correspond to the plurality of data regions, respectively, for managing priorities of the data regions for each of the plurality of processes, and a second management list that includes a plurality of second entries corresponding to the first entries for a process that uses the first data size, for managing priorities of first data of the first data size held in the data regions.

Abstract: A non-transitory computer-readable recording medium stores an adjustment program for causing a computer to perform a process including: acquiring a computation performance characteristic that indicates a computation performance value that corresponds to each adjustable dimension, through computation in which a cache memory in a processor that includes the cache memory is used; extracting, by using the computation performance characteristic, an adjustment condition for adjusting an adjustable dimension for which a decrease in computation performance due to a cache miss caused by a cache-line conflict in the cache memory occurs; and inserting adjustment processing based on the adjustment condition into a specific program that is executed by the processor and uses the adjustable dimension.

Abstract: Systems and methods for computer memory management by a memory coordinator and a plurality of memory consumers. An urgency and memory quota of each memory consumer is initialized by the memory coordinator, which then adjusts the memory quota of each memory consumer such that the sum of the memory quota of each memory consumer does not exceed a finite amount of computer memory. Each memory consumer adjusts its memory usage in response to the quota input and urgency input from the memory coordinator.

Abstract: A device includes a scoreboard and a processor. The scoreboard includes scoreboard entries configured to store information regarding one or more uncompleted memory access operations. The scoreboard also includes a dependency matrix configured to store dependency information corresponding to the scoreboard entries. The processor is configured to retrieve a first memory access instruction that indicates a first address range of a first memory access operation, and to add an indication of the first memory access instruction to a first scoreboard entry. The processor is further configured to, based on determining that the first address range at least partially overlaps a second address range associated with a second scoreboard entry that corresponds to a second memory access instruction, set an element of the dependency matrix to have a has-dependency value indicating a dependency of the first scoreboard entry on the second scoreboard entry.

Abstract: Logical to physical tables each including logical to physical address translations for first logical addresses can be stored. Logical to physical table fragments each including logical to physical address translations for second logical address can be stored. A first level index can be stored. The first level index can include a physical table address of a respective one of the logical to physical tables for each of the first logical addresses and a respective pointer to a second level index for each of the second logical addresses. The second level index can be stored and can include a physical fragment address of a respective logical to physical table fragment for each of the second logical addresses.