Patents Examined by Edward J Dudek
  • Patent number: 11836390
    Abstract: A storage services device includes: a first processor that provides first server services for a server having a second processor that is coupled to a second storage and that provides second server services of the server and a storage controller coupled to a first storage of the server that transmits information about the first storage to the first processor. The storage services device is disposed in the server and disaggregates, within the server, the first server services from the second server services.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: December 5, 2023
    Assignee: Dell Products L.P.
    Inventors: Balasubramanian Chandrasekaran, Lucas Avery Wilson, Dharmesh M. Patel
  • Patent number: 11836517
    Abstract: A method includes receiving a memory access request comprising a first memory address and translating the first memory address to a second memory address using a first page table associated with the first virtual machine. The first page table indicates whether the memory of the first virtual machine is encrypted. The method further includes determining that the first virtual machine is nested within a second virtual machine and translating the second memory address to a third memory address using a second page table associated with the second virtual machine. The second page table indicates whether the memory of the second virtual machine is encrypted.
    Type: Grant
    Filed: October 6, 2022
    Date of Patent: December 5, 2023
    Assignee: Red Hat, Inc.
    Inventors: Michael Tsirkin, Karen Lee Noel
  • Patent number: 11829258
    Abstract: A drive recorder includes: a recording control unit that records vehicle information in a first recording medium; a deterioration detection unit that detects deterioration of the first recording medium; a backup processing unit that performs a backup process of transferring at least a portion of the vehicle information recorded in the first recording medium to a second recording medium in response to detection of deterioration of the first recording medium; a suspension determination unit that determines whether it is possible to suspend recording the vehicle information in the first recording medium, based on the vehicle information; and an initialization processing unit that initializes the first recording medium when it is determined that the backup process is completed and it is possible to suspend recording the vehicle information.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: November 28, 2023
    Assignee: JVCKENWOOD Corporation
    Inventors: Yuichi Murakami, Yusuke Yamaguchi
  • Patent number: 11829622
    Abstract: A method for selectively untying at least one of compression related links to a stale reference chunk, the method may include determining whether a compression effectiveness condition is fulfilled in relation to a set of referring chunks that are compressed using the stale reference chunk and are linked to the to the stale reference chunk by the compression related links; wherein the compression effectiveness condition is responsive to, at least, a number of the referring chunks of the set; and untying the at least one compression related links to the stale reference chunks when the compression effectiveness condition is not fulfilled.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: November 28, 2023
    Assignee: VAST DATA LTD.
    Inventors: Lior Klipper, Alon Berger, Itay Khazon, Yogev Vaknin
  • Patent number: 11829625
    Abstract: Embodiments of the present disclosure relate to managing communications between slices on a storage device engine. Shared slice memory of a storage device engine is provisioned for use by each slice of the storage device engine. The shared slice memory is a portion of total storage device engine memory. Each slice's access to the shared memory portion is controlled.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: November 28, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Rong Yu, Jingtong Liu, Peng Wu
  • Patent number: 11822796
    Abstract: A method includes detecting a power-up event associated with a memory sub-system comprising a plurality of blocks of memory cells having blocks of memory cells associated therewith, responsive to detecting the power-up event and prior to receipt of signaling indicative of a host initiation sequence, determining that a block of memory cells associated with a respective block among the plurality of blocks of memory cells is an open virtual block of memory cells, determining that the respective block associated with the open virtual block of memory cells exhibits greater than a threshold health characteristic value, and selectively performing a media management operation of a respective block of memory cells associated with the open virtual block of memory cells in response to the determination that the respective block exhibits greater than the threshold health characteristic value.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: November 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Tao Liu, Xiangang Luo
  • Patent number: 11809333
    Abstract: A device comprising: storage comprising a group of partitions, and a controller operable to place data into a selected one of the partitions, and to evict existing data from the selected partition when already occupied. The eviction is performed according to an eviction policy. According to this, each partition has an associated age indicator, each age indicator is operable to cycle through a sequence of J steps. Each age indicator is able to run ahead of the current oldest age indicator, but only as long as the age indicators of all the partitions in the group, between them, form a consecutive run of no more than K consecutive steps in the sequence, where K<J?1. The selected partition for eviction is one of the partitions in the group with the oldest age indicator.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: November 7, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Julio Gago Alonso
  • Patent number: 11803314
    Abstract: In at least one embodiment, processing can include receiving a metadata (MD) update for a MD page, wherein the MD update has an associated type; determining whether the type is a custom MD type; responsive to determining the type is a custom MD type, performing first processing including: determining a custom bucket handle for the MD update based at least in part on the type and a logical index (LI) uniquely identifying the MD page; and applying the MD update to a custom bucket associated with the custom bucket handle; and responsive to determining the type is a custom MD type, performing second processing including: determining a regular bucket handle for the MD update based at least in part on the LI of the MD page; and applying the MD update to a regular bucket associated with the regular bucket handle.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: October 31, 2023
    Assignee: Dell Products L.P.
    Inventors: Vladimir Shveidel, Bar David, Ami Sabo
  • Patent number: 11803323
    Abstract: A cascaded memory system includes a memory module having a primary interface coupled to a memory controller via a first communication channel and a secondary interface coupled to a second memory module via a second communication channel. The first memory module buffers and repeats signals received on the primary and secondary interfaces to enable communications between the memory controller and the secondary memory module.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: October 31, 2023
    Assignee: RAMBUS INC.
    Inventors: Christopher Haywood, Frederick A. Ware
  • Patent number: 11803484
    Abstract: A processor applies a software hint policy to a portion of a cache based on access metrics for different test regions of the cache, wherein each test region applies a different software hint policy for data associated with cache entries in each region of the cache. One test region applies a software hint policy under which software hints are followed. The other test region applies a software hint policy under which software hints are ignored. One of the software hint policies is selected for application to a non-test region of the cache.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: October 31, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Paul Moyer
  • Patent number: 11803331
    Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: performing a first write operation to store first data to a first physical unit; recording first unit management information corresponding to the first write operation, wherein the first unit management information reflects a usage order of first used physical units, and the first used physical units include the first physical unit; performing data merge operation to copy at least a part of data stored in the first physical unit to a second physical unit; and after the data merge operation is performed, recording second unit management information according to the first unit management information, wherein the second unit management information reflects a usage order of second used physical units. The second used physical units include the second physical unit but do not include the first physical unit.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: October 31, 2023
    Assignee: Hefei Core Storage Electronic Limited
    Inventors: Wan-Jun Hong, Yang Zhang, Wenbin Tao, Hao Yang, Mengkai Wu, Yankai Dai
  • Patent number: 11797233
    Abstract: A data relay device including: a storage circuit that stores, for each of storages, an upper limit number indicating a number of input/output (I/O) commands that are transmittable; a relay circuit that relays data transmitted and received between one or more control devices and the storages; and a control circuit that performs: counting, for each storage, a number of commands indicating a number of the I/O commands that have been transmitted via the relay circuit and for which no response has been returned from transmission destination storages among the storages; in response to a request to retry transmission of the I/O commands from one storage among the storages, registering a first number in the storage circuit as the upper limit number of commands that corresponds to the one storage, the first number being a number obtained by subtracting one from a counted value of the number of commands.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: October 24, 2023
    Assignee: FUJITSU LIMITED
    Inventor: Junichi Ogawa
  • Patent number: 11797184
    Abstract: Embodiments of the present invention relates to an SD card hot plugging identification method, an SD card identification module and an electronic device. The SD card identification module includes: an interrupt generation unit configured to trigger an interrupt message according to an SD card inserting or ejecting behavior; a message parsing unit configured to determine an SD card status according to the interrupt message during operation of a device; and a device operating unit configured to perform a corresponding SD card operation according to the SD card status determined by the message parsing unit and a device node search unit.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: October 24, 2023
    Assignee: AUTEL ROBOTICS CO., LTD.
    Inventor: Zhaozao Li
  • Patent number: 11789629
    Abstract: A system includes a processing device and trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred. The system can further include a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion having a first endurance characteristic and a first reliability characteristic associated therewith. The memory device can further include a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can have a second endurance characteristic and a second reliability characteristic associated therewith. The processing device can perform operations including writing received data sequentially to the cyclic buffer partition portion and writing, based at least in part on the determination that the trigger event has occurred, data from the cyclic buffer partition portion to the snapshot partition portion.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: October 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Niccolo' Righetti, Jeffrey S. McNeil, Jr., Akira Goda, Todd A. Marquart, Mark A. Helm, Gil Golov, Jeremy Binfet, Carmine Miccoli, Giuseppina Puzzilli
  • Patent number: 11782646
    Abstract: Provided herein may be a memory device and a memory system having the memory device. The memory system includes a memory device including a plurality of memory blocks, each including chunk blocks, and page buffer blocks respectively coupled to the chunk blocks, and a memory controller configured to, based on chunk block status information indicating whether each of the chunk blocks is one of a pass chunk block and a bad chunk block, control the memory device to perform an operation corresponding to a command on merged pass chunk blocks obtained by merging pass chunk blocks coupled to different page buffer blocks among pass chunk blocks included in memory blocks, each of the memory blocks including both the pass chunk block and the bad chunk block.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: October 10, 2023
    Assignee: SK hynix Inc.
    Inventor: Seung Hyun Chung
  • Patent number: 11775188
    Abstract: An apparatus with a solid state drive (SSD) configured to manage storage resources for proof of space activities. The SSD has a host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands and the write commands. In response to an indication of a storage space request for the host system, the apparatus identifies an application using a proof of space plot stored in a portion of the solid state drive, requests the application to separate from the proof of space plot, and then delete a namespace in which the proof of space plot is stored to release storage resources occupied by the proof of space plot to meet the storage space request.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: October 3, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Luca Bert, Joseph Harold Steinmetz
  • Patent number: 11775219
    Abstract: Examples of electronic devices are described herein. In some examples, an electronic device includes a flash memory. In some examples, the electronic device includes a host memory to store an access control structure to access the flash memory. In some examples, the electronic device includes a first circuitry coupled to the host memory and the flash memory. In some examples, the first circuitry is to read the access control structure in the host memory to determine when to access the flash memory.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: October 3, 2023
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Wei Ze Liu, Khoa Dang Huynh, Rosilet Retnamoni Braduke
  • Patent number: 11775433
    Abstract: A method to store a data value onto a cache of a storage hierarchy. A range of a collection of values that resides on a first tier of the hierarchy is initialized. The range is partitioned into disjointed range partitions; a first subset of which is designated as cached; a second subset is designated as uncached. The collection is partitioned into a subset of uncached data and cached data and placed into respective partions. The range partition to which the data value belongs (i.e. the target range partition) is identified as being cached. If the cache is full all cached range partitions that do not contain the data value are designated as uncached. All values that lie in the cached range partitions designated as uncached are evicted. The data value is then inserted into the target range partition, and copied to the first tier.
    Type: Grant
    Filed: October 20, 2022
    Date of Patent: October 3, 2023
    Assignee: Kinaxis Inc.
    Inventor: Angela Lin
  • Patent number: 11775183
    Abstract: An operation method of a storage device, which includes a nonvolatile memory device, includes receiving a first key-value (KV) command including a first key from an external host device; transmitting a first value corresponding to the first key from the nonvolatile memory device to the external host device as first user data, in response to the first KV command; receiving a second KV command including a second key, from the external host device; and performing a first administrative operation based on a second value corresponding to the second key, in response to the second KV command. The first KV command and the second KV command are KV commands of a same type.
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: October 3, 2023
    Inventors: Byoung Geun Kim, Keunsan Park, Sangyoon Oh, Byung-Ki Lee, Yonghwa Lee, Jooyoung Hwang
  • Patent number: 11768764
    Abstract: A wear-leveling process for a memory subsystem selects a source chunk to be removed from a usable address space of the memory subsystem to distribute wear across all available chunks in the memory subsystem. The memory subsystem has a plurality of non-volatile memory components. The plurality of non-volatile memory components includes a plurality of chunks including at least one chunk in an unusable address space of the memory subsystem. The wear-leveling process copies valid data of the source chunk to a destination chunk in the unusable address space of the memory subsystem and assigns the destination chunk to a location in the usable address space of the memory subsystem occupied by the source chunk.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: September 26, 2023
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Samuel E. Bradshaw, Justin Eno