Abstract: The present invention optimizes the performance of integrated circuits by adjusting the circuit operating voltage using feedback on process/product parameters. To determine a desired value for the operating voltage of an integrated circuit, a preferred embodiment provides for on-wafer probing of one or more reference circuit structures to measure at least one electrical or operational parameter of the one or more reference circuit structures; determining an adjusted value for the operating voltage based on the measured parameter; and establishing the adjusted value as the desired value for the operating voltage. The reference circuit structures may comprise process control monitor structures or structures in other integrated circuits fabricated in the same production run. In an alternative embodiment, the one or more parameters are directly measured from the integrated circuit whose operating voltage is being adjusted.

Abstract: The present invention provides a semiconductor device, including: a first semiconductor chip, and a second semiconductor chip connected to the first semiconductor chip through a plurality of bumps having not only a number of main bumps necessary for operation between the chips but also a predetermined number of measurement and control input bumps. Each of the first and second chips includes a plurality of measurement path switches individually connected to the main bumps, a plurality of current path switches connected to connecting points between the main bumps and the measurement path switches, and a control circuit for the measurement path switches, the first semiconductor chip further including a plurality of measurement and control terminals for inputting a control signal of the control circuit and supplying fixed current to be supplied to the current path switches and then measuring the voltage at the connecting points.

Abstract: A semiconductor device having a circuit for detecting a defective connection to the semiconductor device. A semiconductor device including multiple internal circuits; multiple pads respectively connected to the internal circuits; and a contact failure detector coupled between the pads and a common node and configured to detect contact failures between tips of a probe card and the pads.

Abstract: A system for testing with an automated test equipment (ATE) includes a tester having at least one test resource, a tandem handler, and a mux relay that switchably connects the test resource, via parallel connections, to either one of dual sockets at each instant of testing. The handler has first and second manipulator arms. Each arm operates as to a particular one of the respective sockets, to retrieve a next device to be tested and position the device in the socket (while testing is performed on a device in the other socket), to disposition the device from the socket once testing is completed as to the device in the socket, and thereafter repeat until all staged devices for testing have been tested (or an interruption of testing otherwise occurs). The mux relay switches between sockets in response to the tandem handler acting as a master and the tester as slave.

Abstract: To reduce the time to make measurements and the noise in measurements obtained by probing a device supported on surface of a thermal chuck in a probe station, a conductive member is arranged to intercept current coupling the thermal unit of the chuck to the surface supporting the device. The conductive member is capacitively coupled to the thermal unit but free of direct electrical connection thereto.

Abstract: In a method for detecting an inverter hardware failure in an electric power train comprising high voltage cables, at least one electric machine and at least two inverter legs with two power electronic switches respectively for pulse-width-modulating a DC voltage from a high voltage battery for energizing the at least one electric machine, and including at least one mid-pack voltage sensor for detecting isolation faults, wherein all power electronic switches are demanded to open; at least one of the power electronic switches of one of the inverter legs is opened and closed at a time at a given duty cycle and a given frequency; a mid-pack voltage is measured using the mid-pack voltage sensor; the closed switch is identified as functional in case a common mode voltage is detected by the mid-pack voltage sensor or otherwise the closed switch is identified as non-functional.

Abstract: In an electronic testing machine including at least one test module having a plurality of contacts for testing electronic components, the improvement of a contact alignment tool for aligning the contacts is taught. The tool includes a body to be positioned relative to the machine such that the body can be radially indexed along a path to a test position proximate the contacts and a plurality of circuits associated with the body. Each circuit includes at least one output signal connection and at least one open contact station. Each station is defined by at least one open circuit trace pattern and is closed by the contacts when the body is located at the test position and the contacts are properly aligned. A method and apparatus for aligning contacts of an electronic testing machine are also taught.

Abstract: An energy consumption meter includes a first input for providing a first input signal derived from a voltage, a first analog-to-digital (A/D) converter electrically connected to the first input to generate a first output signal based on the first input signal, a second input for providing a second input signal derived from a current, a second A/D converter electrically connected to the second input to generate a second output signal based on the second input signal, a multiplier to combine signals corresponding to the first and second output signals, and a phase evaluation block having two inputs that are electrically connected to the first input and to the second input. The phase evaluation block measures a phase difference that corresponds to a phase difference between the first input signal and the second input signal. A phase correction block corrects for the phase difference in one of the first output signal and the second output signal.

Abstract: An electronic device under test (DUT) may be incorporated into a circuit having a voltage limiter connected in parallel with the DUT. The circuit includes a controlled current source having an output current connected in series with the DUT. The voltage limiter is characterized in that, when the output current is such that the voltage across the DUT (Vdut) would exceed a particular maximum voltage Vmax, without the voltage limiter in place, at least a portion of the output current flows through the voltage limiter, so as to limit Vdut to be less than or equal to Vmax. When the output current is such that Vdut would be less than or equal to Vmax, current does not flow through the voltage limiter. The circuit may include a plurality of DUTs, each DUT connected in series with the output current of a controlled current source, with a voltage limiter connected in parallel with each DUT.

Abstract: A probe navigation method, a navigation device, and a defect inspection device wherein in a charged particle beam system provided with probes for electrical characteristics evaluation, probing can be easily carried out regardless of the equipment user's level of skill are provided. To attain this object, probes and a test piece stage on which a test piece is placed are driven by independent driving means. Further, a large stage driving means which integrally drives the probes and the test piece stage is provided. In addition, CAD navigation is adopted. This enhances the equipment users' convenience during probing.

Abstract: A semiconductor driver circuit includes impedance units for generating impedances at data pads, independently of each-other. Thus, signal swing widths of data signals generated at the data pads may be easily adjusted to be substantially equal for high operating speed. The semiconductor driver circuit also includes switching units for uncoupling at least one of the impedance units from at least one of the data pads for enhanced testing of the data pads.

Abstract: Method and system for periodically measuring the junction temperature of a semiconductor device. The junction exited by at least two sequential predetermined currents of different magnitudes. The voltage response of the junction to the at least two currents is measured and the temperature of the junction is calculated, while substantially canceling ohmic effects, by using the voltage response and a correction factor obtained by periodically. Whenever desired, the junction is exited by a set of at least four sequential different currents having known ratios. The voltage response to the set is measured and the correction factor is calculated by using each voltage response to the set.

Abstract: The connection between a PTC element 22a corresponding to each semiconductor IC 11a and a power-supply line 25a is performed via a relay, a high voltage is supplied to the power-supply line 25a by sequentially turning on the relays, and a high voltage is supplied to each PTC element 22a in order, whereby it is possible to trip beforehand a PTC element 22a connected to a DC-defective semiconductor IC 11a. In this state, wafer level burn-in is performed together, which enables the PTC element 22a to be positively tripped during the burn-in for the DC defect of the semiconductor IC 11a, with the result that it is possible to increase the reliability of the burn-in.

Abstract: The present invention is directed to a test structure and method to determine the effects of the well proximity effect on the gate threshold voltage of FETs at different distances from the edge of the well.

Abstract: The voltage application probe (54) and the voltage measurement probe (56) are connected to the voltage application pad (74) and the voltage measurement pad (76) of the semiconductor device (70). The voltage application pad (74) and the voltage measurement pad (76) are connected by the conductor (78), measuring the voltage applied to the voltage application pad (74) through the voltage measurement probe (56). The voltage compensation circuit (14) in the voltage development device (10) operates to make the voltage applied to the voltage application pad (74) equal to the set voltage for the voltage development device (10). Even when the resistance between the voltage application probe (54) and the voltage application pad (74) increases, the accurate setting voltage is applied to the voltage application pad (74).

Abstract: A high-precision Rogowski current transformer, the Rogowski coil is realized in a single printed circuit board while maintaining both the outside field rejection of a traditional Rogowski coil, and the increased output voltage similar to the multiple printed circuit board Rogowski coil arrangements.

Abstract: A semiconductor device comprises IC chips, each having semiconductor elements and pad regions, formed on a substrate, and conductor patterns for detecting displacement of a probe needle during a probing test of the IC chips. The conductor patterns each have an inner conductor and an outer conductor disposed in spaced-apart concentric relationship to one another, and the conductor patterns may be formed on the IC chips or on the substrate in a scribe region between adjacent IC chips. The distance between the inner and outer conductors is smaller than the size of the point or end tip of the probe needle. During a probing test, the probe needle is placed in contact with only the inner conductor, and slight displacement of the probe needle such that it moves into contact with both the inner and outer conductors during the probing test is detected by measuring an electricl characteristic between the two conductors so that corrective action can be taken.

Abstract: A semiconductor inspection apparatus includes a force probe applying voltage to a semiconductor device, and a sense probe detecting voltage of the semiconductor device, in which the force probe is contacted with an electrode pad of the semiconductor device and the force probe and the sense probe are contacted with each other to measure electric characteristics of the semiconductor device, and the force probe and the sense probe are arranged substantially on the same line when seen from a vertical direction with respect to an electrode surface (principal surface) of the semiconductor device.

Abstract: A probe card assembly can comprise an interface, which can be configured to receive from a tester test signals for testing an electronic device. The probe card assembly can further comprise probes for contacting the electronic device and electronic driver circuits for driving the test signals to ones of the probes.

Abstract: Systems and methods for evaluating electromagnetic interference that may be employed, for among other things, to evaluate electronic system immunity to radiated electromagnetic fields and/or to identify particular electronic system areas that are susceptible to electromagnetic radiation.