Abstract: A light emitting device package can include first and second frames spaced apart from each other; a package body including a body portion disposed between the first and second frames; a light emitting device including first and second electrode pads; a first through hole in the first frame; a second through hole in the second frame; a conductive material disposed in the first and second through holes; and an intermetallic compound layer disposed between the conductive material and the first frame, and between the conductive material and the second frame, in which the first electrode pad of the light emitting device overlaps with the first through hole in the first frame, the second electrode pad of the light emitting device overlaps with the second through hole in the second frame, and the first and second electrode pads are spaced apart from each other.

Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with a first silicon nitride layer. The first region is covered with a protection layer that can be etched selectively with respect to the silicon nitride. The structure is covered with a second silicon nitride layer. The trenches are etched through the second and first silicon nitride layers and filled with a filling silicon oxide to a level situated above the protection layer. The second silicon nitride layer and the part of the first silicon nitride layer situated on the second region are selectively removed and the protection layer is removed. The filling oxide is selectively etched by wet etching, thus resulting in pits on the surface of the filling oxide around the second region.

Abstract: A display apparatus can includes a first substrate including an active area, a non-active area surrounding the active area, and a bending part bent in a curve shape; a pixel array layer disposed in the active area of the first substrate; a second substrate disposed on the pixel array layer in which the pixel array layer is between the first substrate and the second substrate; and a cover layer disposed in the non-active area of the first substrate, the cover layer covering a side surface of the second substrate, in which the cover layer is disposed in a remaining portion of the non-active area except for an area of the non-active area that overlaps with the bending part.

Abstract: A method for fabricating a semiconductor structure on a semiconductor wafer is disclosed. A semiconductor wafer having a first region, a second region, and a wafer bevel region is provided. The wafer bevel region has a silicon surface. A first semiconductor structure is formed in the first region and a second semiconductor structure is formed in the second region. The semiconductor wafer is subjected to a bevel plasma treatment to form a blocking layer only in the wafer bevel region. A silicidation process is then performed to form a silicide layer only in the first region and the second region.

Abstract: To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a resistive memory device is provided. The resistive memory device includes an active region having resistance properties that can be modified to store one or more data bits in the resistive memory device, and at least one sidewall portion of the active region comprising a dopant configured to suppress conductance paths in the active region proximate to the at least one sidewall portion. The resistive memory device includes terminals configured to couple the active region to associated electrical contacts.

Abstract: A crystalline oxide semiconductor thin film that is composed mainly of indium oxide and comprises surface crystal grains having a single crystal orientation.

Abstract: A semiconductor light-emitting device comprises: an insulating base, a current diffusion layer, light-emitting structure layers and an insulating layer. The current diffusion layer includes: a first electrode connecting part, a second electrode connecting part, N contact parts and N+1 flat parts. N+1 light-emitting structure layers are correspondingly disposed on the N+1 flat parts, and each of the N+1 light-emitting structure layers includes: a first semiconductor layer, an active layer and a second semiconductor layer sequentially stacked on a corresponding flat part. N grooves are formed on a side of the second semiconductor layer away from the active layer, depth of the N grooves is less than the thickness of the second semiconductor layer, and the N contact parts correspond to the N grooves.

Abstract: Various embodiments of the present application are directed towards a method for workpiece-level alignment with low alignment error and high throughput. In some embodiments, the method comprises aligning a first alignment mark on a first workpiece to a field of view (FOV) of an imaging device based on feedback from the imaging device, and further aligning a second alignment mark on a second workpiece to the first alignment mark based on feedback from the imaging device. The second workpiece is outside the FOV during the aligning of the first alignment mark. The aligning of the second alignment mark is performed without moving the first alignment mark out of the FOV. Further, the imaging device views the second alignment mark, and further views the first alignment mark through the second workpiece, during the aligning of the second alignment mark. The imaging device may, for example, perform imaging with reflected infrared radiation.

Abstract: A method of planarizing a semiconductor device includes forming a first region and a second region on a semiconductor substrate. The first region has a larger thickness than a thickness of the second region. An interlayer dielectric layer is conformally deposited on the first region and the second region. A photoresist is formed on the second region. A bottom anti-reflective coating layer is formed on the photoresist, first region and second region. A planarization process is performed to the semiconductor substrate. The planarization process to the first region and the second region includes removing portions of the interlayer dielectric layer, the photoresist and the BARC layer.

Abstract: A semiconductor device includes a base substrate. A first thin-film transistor is disposed on the base substrate. The first thin-film transistor includes a first input electrode, a first output electrode, a first semiconductor pattern disposed below a first insulating layer, and a first control electrode disposed on the first insulating layer and below a second insulating layer. A second thin-film transistor includes a second input electrode, a second output electrode, a second semiconductor pattern disposed on the second insulating layer, and a second control electrode disposed on an insulating pattern formed on the second semiconductor pattern and exposes a portion of the second semiconductor pattern. The first semiconductor pattern includes a crystalline semiconductor. The second semiconductor pattern includes an oxide semiconductor. The first semiconductor pattern, the first control electrode, the second semiconductor pattern, and the second control electrode are overlapped.

Abstract: A source/drain contact includes a first portion arranged on a substrate and extending between a first gate and a second gate; a second portion arranged on the first portion and extending over the first gate and the second gate, the second portion including a partially recessed liner and a metal disposed on the partially recessed liner, and the partially recessed liner arranged on an endwall of the second portion and in contact with the first portion; and an oxide disposed around the second portion and on the first gate and the second gate.

Abstract: A method of forming a 3D Hall effect sensor and the resulting device are provided. Embodiments include forming a p-type well in a substrate; forming a first n-type well in a first region surrounded by the p-type well in top view; forming a second n-type well in a second region surrounding the p-type well; providing n-type dopant in the first and second n-type wells; and providing p-type dopant in the p-type well and the first n-type well.

Abstract: A light-emitting device includes a light-emitting element that includes a layered structure including a semiconductor layer and a pair of electrodes on a first main surface of the layered structure, a light-transmissive member on a second main surface of the layered structure, the second main surface being opposite to the first main surface, a covering member covering lateral surfaces of the light-emitting element and the first main surface of the layered structure except for at least part of the pair of electrodes, a pair of first metal layers on the first main surface of the light-emitting element, the pair of first metal layers covering a surface of the covering member and being respectively connected with the pair of electrodes, and at least one second metal layer separated from the first metal layers.

Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.

Abstract: A vFET includes a first impurity region doped with first impurities at an upper portion of the substrate. A first diffusion control pattern is formed on the first impurity region. The first diffusion control pattern is configured to control the diffusion of the first impurities. A channel extends in a vertical direction substantially orthogonal to an upper surface of the substrate. A second impurity region is doped with second impurities on the channel. A second diffusion control pattern is between the channel and the second impurity region. The second diffusion control pattern is configured to control the diffusion of the second impurities. A gate structure is adjacent to the channel.

Abstract: A tilted nanowire structure is provided which has an increased gate length as compared with a horizontally oriented semiconductor nanowire at the same pitch. Such a structure avoids complexity required for vertical transistors and can be fabricated on a bulk semiconductor substrate without significantly changing/modifying standard transistor fabrication processing.

Abstract: A side view surface mount light emitting device is disclosed. The light emitting device comprises a side oriented package comprising a floor and a plurality of light emitting diodes (LEDs) mounted on the floor. The device further includes a plurality of contact pins in electrical contact, such that the plurality of contact pins protrude from a side of the package, in which at least one of the contact pins is oriented in a direction opposite the remaining contact pins. The LEDs of the device are disposed to emit light in a direction parallel to said mount surface. Some configurations also include a plurality of bond pads, on or a part of the floor, to facilitate electrical connection between the LEDs and the contact pins, in which adjacent bond pads have a tapered shape such that the widest portion of a first bond pad is adjacent to the narrowest portion of a second bond pad. Displays including such devices are also disclosed.

Abstract: There is provided semiconductor devices and methods of forming the same, the semiconductor devices including: a first semiconductor element having a first electrode; a second semiconductor element having a second electrode; a Sn-based micro-solder bump formed on the second electrode; and a concave bump pad including the first electrode opposite to the micro-solder bump, where the first electrode is connected to the second electrode via the micro-solder bump and the concave bump pad.

Abstract: An organic light emitting diode device comprising: a light emitting layer or layers combining both an emissive material comprising a boron subphthalocyanine, or first emitting layer component, that emits substantially orange light; and an emissive material emitting blue light, or second emitting layer component; wherein in combination, the first emitting layer component and the second emitting layer component, in combination, produces an overall white or near-white light emission.

Abstract: A semiconductor device structure includes a region of semiconductor material having an active region and a termination region. An active structure is disposed in the active region and a termination structure is disposed in the termination region. In one embodiment, the termination structure includes a termination trench and a conductive structure within the termination trench and electrically isolated from the region of semiconductor material by a dielectric structure. A dielectric layer is disposed to overlap the termination trench to provide the termination structure as a floating structure. A Schottky contact region is disposed within the active region. A conductive layer is electrically connected to the Schottky contact region and the first conductive layer extends onto a surface of the dielectric layer and laterally overlaps at least a portion of the termination trench.