Abstract: In some embodiments, a method for forming an integrated chip (IC) is provided. The method incudes forming an interlayer dielectric (ILD) layer over a substrate. A first opening is formed in the ILD layer and in a first region of the IC. A second opening is formed in the ILD layer and in a second region of the IC. A first high-k dielectric layer is formed lining both the first and second openings. A second dielectric layer is formed on the first high-k dielectric layer and lining the first high-k dielectric layer in both the first and second regions. The second high-k dielectric layer is removed from the first region. A conductive layer is formed over both the first and second high-k dielectric layers, where the conductive layer contacts the first high-k dielectric layer in the first region and contacts the second high-k dielectric in the second region.

Abstract: A semiconductor arrangement comprises a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement comprises a second semiconductor column projecting from the substrate region. The second semiconductor column is separated a first distance from the first semiconductor column. The first distance is between about 10 nm to about 30 nm.

Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.

Abstract: A layer according to one embodiment of the present invention may exhibit a first number of electron states in a low-level electron energy range in a conduction band, and exhibit a second number of electron states in a high-level electron energy range higher than the low-level electron energy level in the conduction band, wherein localized states may exist between the low-level electron energy range and the high-level electron energy level.

Abstract: Disclosed is a display device capable of preventing a problem related with a bluish image at a lateral viewing angle by the use of optical-path adjustment film on an upper surface of a display panel, wherein the display device may include a display panel, and an optical-path adjustment film on the display panel, wherein the optical-path adjustment film includes a plurality of dome patterns, and a cover layer on the plurality of dome patterns, wherein a refractive index of the plurality of dome patterns is different from a refractive index of the cover layer.

Abstract: Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes forming a first type of fin sidewall spacers and a second type of fin sidewall spacers. The first type of fin sidewall spacers are formed on two sidewall surfaces of a third fin portion group along a width direction of the third fin portions and two sidewall surfaces of a fourth fin portion group along a width direction of the fourth fin portions. The second type of fin sidewall spacers are formed between adjacent third fin portions and sidewall surfaces of the third fin portions and between adjacent fourth fin portions and on sidewall surfaces of the fourth fin portions. Top surfaces of the first type of fin sidewall spacers are higher than top surfaces of the second type of fin sidewall spacers and top surfaces of the third fin portions and the fourth fin portions.

Abstract: A photoelectric detection structure, a manufacturing method therefor, and a photoelectric detector. The photoelectric detection structure includes: a base substrate; an electrode strip, which is located on the base substrate; a semiconductor layer, which is located at a side of the base substrate that faces the electrode strip; an insulating layer, which is located between the electrode strip and the semiconductor layer, the insulating layer including a thickness-increased portion, and the thickness-increased portion being located on at least one edge of the electrode strip.

Abstract: A semiconductor light emitting device includes a first semiconductor layer of a first conductivity type on a substrate, an active layer on the first semiconductor layer, a second semiconductor layer of a second conductivity type on the active layer, the second semiconductor layer being doped with magnesium (Mg), and having an upper surface substantially parallel to an upper surface of the substrate and a side surface inclined with respect to the upper surface of the substrate, and a third semiconductor layer of the second conductivity type on the second semiconductor layer, the third semiconductor layer being doped with magnesium (Mg) at a concentration different from that of the second semiconductor layer, and having an upper surface substantially parallel to the upper surface of the substrate and a side surface inclined with respect to the upper surface of the substrate.

Abstract: A semiconductor device structure includes a region of semiconductor material having an active region and a termination region. An active structure is disposed in the active region and a termination structure is disposed in the termination region. In one embodiment, the termination structure includes a termination trench and a conductive structure within the termination trench and electrically isolated from the region of semiconductor material by a dielectric structure. A dielectric layer is disposed to overlap the termination trench to provide the termination structure as a floating structure. A Schottky contact region is disposed within the active region. A conductive layer is electrically connected to the Schottky contact region and the first conductive layer extends onto a surface of the dielectric layer and laterally overlaps at least a portion of the termination trench.

Abstract: A semiconductor memory device includes a channel layer and a gate electrode. A first insulating layer is between the semiconductor layer and the gate electrode. A second insulating layer is between the first insulating layer and the gate electrode. A storage region is between the first insulating layer and the second insulating layer. The storage region comprises metal or semiconductor material. A coating layer comprises silicon and nitrogen and surrounds the storage region. The coating layer is between the storage region and the second insulating layer and between the storage region and the first insulating layer.

Abstract: A source-level sacrificial layer and an alternating stack of insulating layers and sacrificial material layers are formed over a substrate. Memory openings are formed through the alternating stack, and a source cavity is formed by removing the source-level sacrificial layer. A memory film is formally formed by a conformal deposition process, and a source contact layer is formed in the source cavity. Vertical semiconductor channels and drain regions are formed in remaining volumes of the memory openings on sidewalls of the source contact layer. A backside contact via structure is formed through the alternating stack and directly on a sidewall of the source contact layer.

Abstract: A display device includes: a substrate comprising a first region and a second region bent relative to the first region; a plurality of first pixels at the first region, each of the first pixels comprising a first light-emitting diode (LED), the first LED comprising a pixel electrode, an emission layer for emitting light of a first color, and a counter electrode; a plurality of second pixels at the second region, each of the second pixels comprising a second LED, the second LED comprising a pixel electrode, an emission layer configured to emit the first color, and a counter electrode; and an optical resonance layer at the second region corresponding to the second LED.

Abstract: A multispectral image sensor includes a semiconductor layer and a number of pixels formed inside and on top of the semiconductor layer. Each pixel includes an active photosensitive area formed in a portion of the semiconductor layer laterally delimited by peripheral insulating walls. The pixels include a first pixel of a first type and a second pixel of a second type. The portion of semiconductor layer of the first pixel has a first lateral dimension selected to define a lateral cavity resonating at a first wavelength and the portion of semiconductor layer of the second pixel has a second lateral dimension different from the first lateral dimension. The second lateral dimension is selected to define a lateral cavity resonating at a second wavelength different from the first wavelength.

Abstract: A laterally diffused metal oxide semiconductor (LDMOS) device includes a substrate having a p-epi layer thereon, a p-body region in the p-epi layer and an ndrift (NDRIFT) region within the p-body to provide a drain extension region. A gate stack includes a gate dielectric layer over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region. A patterned gate electrode is on the gate dielectric. A DWELL region is within the p-body region. A source region is within the DWELL region, and a drain region is within the NDRIFT region. An effective channel length (Leff) for the LDMOS device is 75 nm to 150 nm which evidences a DWELL implant that utilized an edge of the gate electrode to delineate an edge of a DWELL ion implant so that the DWELL region is self-aligned to the gate electrode.

Abstract: The present disclosure provides a thin film transistor (TFT) substrate and a manufacturing method thereof. The TFT substrate include a TFT; a flat layer to cover the TFT; an opening hole defined in the flat layer and corresponding to a drain of the TFT; a bottom of the opening hole to retain a part of the flat layer for forming a flat layer sheet; a first metal layer formed on the flat layer; a first insulating layer formed on the first metal; a second metal formed on the first insulating layer and pass through the flat layer sheet for electrically connecting to the drain.

Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.

Abstract: A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region.

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.

Abstract: The present disclosure relates to a display panel, a manufacturing method thereof, and a display device. The display panel comprises a base substrate, a package cover plat disposed to be parallel to the base substrate, a light-emitting layer between the substrate and the package cover plate, and a main package part, which encapsulates a side surface of the base substrate and a side surface of the package cover plate.

Abstract: A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.