Abstract: A semiconductor device includes: a substrate; a first source/drain region and a second source/drain region spaced apart from each other by a trench in the substrate; and a gate structure in the trench, wherein the gate structure includes: a gate dielectric layer formed on a bottom and sidewalls of the trench; a first gate electrode positioned in a bottom portion of the trench over the gate dielectric layer; a second gate electrode positioned over the first gate electrode; and a dipole inducing layer formed between the first gate electrode and the second gate electrode and between sidewalls of the second gate electrode and the gate dielectric layer.

Abstract: A semiconductor device including at least one fin extending upward from a substrate and a gate on the substrate, wherein the gate includes outer sidewalls, wherein the fin extend through a width of the gate. A spacer material can be adjacent to the outer sidewalls of the gate, wherein a top surface of the spacer material is below the top surface of the gate and above the top surface of the fin. The semiconductor device can also include an epitaxial semiconductor layer over the fins on each side of the spacer material. A low-k dielectric material can be deposited above each epitaxial semiconductor layer. The semiconductor device also includes a dielectric top layer forming a top surface of the transistor, wherein the dielectric top layer seals an air gap between the top surface of the fins and the dielectric top layer.

Abstract: A semiconductor device includes a substrate; a vertical channel structure including a pair of active fins extended in a first direction, perpendicular to an upper surface of the substrate, and an insulating portion interposed between the pair of active fins; an upper source/drain disposed on the vertical channel structure; a lower source/drain disposed below the vertical channel structure and on the substrate; a gate electrode disposed between the upper source/drain and the lower source/drain and surrounding the vertical channel structure; and a gate dielectric layer disposed between the gate electrode and the vertical channel structure. An interval between the gate electrode and the upper source/drain may be smaller than an interval between the gate electrode and the lower source/drain in the first direction.

Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region. The semiconductor device also includes an insulating structure laterally between the first region and the second region in the semiconductor substrate. The insulating structure electrically insulates the first region laterally from the second region in the semiconductor substrate. The semiconductor device further includes a connecting structure at a surface of the semiconductor substrate. The connecting structure contacts at least a sub-structure of the insulating structure and at least one of the first region and the second region. At least a sub-structure of the connecting structure has an electrical resistivity greater than 1*103 ?m and less than 1*1012 ?m.

Abstract: A method is presented for forming a monolithically integrated semiconductor device. The method includes forming a first device including first hydrogenated silicon-based contacts formed on a first portion of a semiconductor material of an insulating substrate and forming a second device including second hydrogenated silicon-based contacts formed on a second portion of the semiconductor material of the insulating substrate. Source and drain contacts of the first device are formed before a gate contact of the first device and a gate contact of the second device is formed before the emitter and collector contacts of the second device. The first device can be a heterojunction field effect transistor (HJFET) and the second device can be a (heterojunction bipolar transistor) HBT. The HJFET and the HBT are integrated in a neuronal circuit and create negative differential resistance by forming a lambda diode.

Abstract: A method of fabricating an LED includes: providing an epitaxial structure having a growth substrate, a first-type semiconductor layer, an active layer and a second-type semiconductor layer; forming an extended electrode and performing thermal treatment to form ohmic contact with the second-type semiconductor layer; providing a temporary substrate bonded with the epitaxial structure, and removing the growth substrate to expose the surface of the first-type semiconductor layer; forming an ohmic contact layer, a mirror layer and a bonding layer over the exposed surface of the first-type semiconductor layer; providing a conductive substrate bonded with the bonding layer, and removing the temporary substrate to expose part of the surface of the second-type semiconductor layer and the extended electrode; forming a roughening surface via etching of the exposed second-type semiconductor layer; and providing a bonding wire electrode forming a closed loop with the extended electrode.

Abstract: A method includes: forming first and second pixel electrodes on a substrate; exposing upper surfaces of the first and second pixel electrodes; forming a pixel defining layer covering edges of the first and second pixel electrodes; sequentially forming a first lift-off layer, a first shape memory alloy layer, and a first photoresist; forming a first opening exposing an upper surface of the first pixel electrode by patterning the first lift-off layer, the first shape memory alloy layer, and the first photoresist; forming, on the first pixel electrode and the first photoresist, a first organic functional layer including a first emission layer; deforming an end portion of the first shape memory alloy layer, in the first opening, in a direction away from a horizontal surface of the substrate; forming a first protection layer over the first organic functional layer; and removing a remainder of the first lift-off layer.

Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a first electrode, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a second electrode, and a third electrode. The first semiconductor region includes a first region and a second region. The second semiconductor region is provided on the second region. The third semiconductor region is provided on a portion of the second semiconductor region. The third electrode is provided on the second semiconductor region and the first semiconductor region. A first layer is provided on the third electrode. The first layer includes at least one selected from the group consisting of titanium, nickel, and vanadium. A second layer is provided on the first layer. The second layer includes silicon and at least one selected from the group consisting of nitrogen and oxygen.

Abstract: A semiconductor device having a hybrid doping distribution and a method of fabricating the semiconductor device are presented. The semiconductor device includes a gate disposed over an active semiconducting region and a first S/D region and a second S/D region each aligned to opposing sides of the gate side walls. The active semiconducting region has a doping profile that includes a first doping region at a first depth beneath the gate and having a first dopant concentration. The doping profile includes a second doping region at a second depth beneath the gate greater than the first depth and having a second dopant concentration less than the first dopant concentration.

Abstract: A semiconductor device includes a stacked body including conductive layers and first insulating layers which are alternately stacked. The stacked body includes, on at least one side thereof, a staircase portion having stairs formed from the conductive layers and the first insulating layers. A second insulating layer different in material from the first insulating layer is provided on an upper surface of the first insulating layer of the staircase portion. The second insulating layer is away from the conductive layer on the same first insulating layer. A third insulating layer is provided on the staircase portion. Contacts are provided in the first, second, and third insulating layers situated in the respective stairs of the staircase portion. The contacts lead from an upper surface of the third insulating layer to the conductive layer under the first insulating layer.

Abstract: According to one embodiment, there is provided a semiconductor device including a semiconductor substrate, a plurality of first columnar bodies having a peripheral edge, each of the columnar bodies spaced from one another on the semiconductor substrate, each including a first conductive layer extending from an upper end thereof in the depth direction of the semiconductor substrate, a base layer deposited about an outer peripheral surface of an upper end of the plurality of first columnar bodies, a gate adjacent to the base layer with a gate insulating film therebetween, a source layer connected to the base layer, and a second columnar body, including a second conductive layer, surrounding an outer peripheral edge of the plurality of first columnar bodies and extending in the depth direction of the semiconductor substrate.

Abstract: A display panel and a display device are provided. The display panel has a display region and a peripheral region surrounding the display region. The display panel includes: a scan driving circuit arranged in the peripheral region; a low-level voltage signal line arranged in the peripheral region and electrically connected to the scan driving circuit; an auxiliary metal line arranged in the peripheral region and electrically connected to the low-level voltage signal line. The peripheral region includes a first and second peripheral region located on opposite sides of the display region in a first direction, and a third and fourth peripheral region located on opposite sides of the display region in a second direction, the first direction being perpendicular to the second direction. The auxiliary metal line at least extends in the first, third and second peripheral region to form a structure partially surrounding the display region.

Abstract: A system and method of providing a coil in an electronic communication device in is disclosed. Multiple dielectric layers are deposited and patterned on a semiconductor substrate or insulating mold compound. The dielectric layers provide conductive contact with a contact pad on the underlying structure. Shielding for the coil, including a seed layer covered by an insulating material, is disposed in a via of a lowermost of the dielectric layers. Grounding of the shielding seed layer is through a contact pad on the substrate or a trace between the dielectric layers. A coil is fabricated over the shielding and a solder mask deposited and patterned to cover and insulate the coil. The coil is fabricated in a via of a dielectric layer immediately below the solder mask or above this dielectric layer. Electrical contact is provided by multiple copper and seed layers in the solder mask and dielectric layers.

Abstract: A semiconductor structure includes a substrate, a plurality of fins disposed over a top surface of the substrate, and a gate stack surrounding a portion of sidewalls of the plurality of fins. The plurality of fins include two or more active device fins comprising a semiconducting material providing vertical transport channels for respective vertical transport field-effect transistors, and two or more edge fins surrounding the two or more active device fins, the two or more edge fins comprising a dielectric material. Thicknesses of one or more layers of the gate stack surrounding the portion of the sidewalls of the two or more edge fins are different than thicknesses of the one or more layers of the gate stack surrounding the portion of the sidewalls of the active device fins. The vertical transport field-effect transistors provided by the active device fins have uniform threshold voltage.

Abstract: A semiconductor device includes a semiconductor body and at least one device cell integrated in the semiconductor body. Each device cell includes a drift region, a source region, and a body region arranged between the source region and the drift region. A gate trench extends from a first surface of the semiconductor body, through the source and body regions and into the drift region. A diode region extends under the gate trench. A pn junction is formed between the diode and drift regions below the gate trench. A gate electrode arranged in the gate trench is dielectrically insulated from the source, body, diode and drift regions by a gate dielectric. A contact trench spaced apart from the gate trench extends from the first surface into the source region. A source electrode arranged in the contact trench adjoins the source region at a sidewall of the contact trench.

Abstract: An organic light emitting display panel and apparatus, and a manufacturing method therefor are provided. The organic light emitting display panel includes a plurality of light emitting units, the light emitting unit includes an anode, a first auxiliary functional structure, a light emitting structure and a cathode, the anode, the first auxiliary functional structure, the light emitting structure and the cathode are successively laminated, and the first auxiliary functional structures of different light emitting units are arranged separate from one another, the anodes of different light emitting units are arranged separate from one another, and the light emitting structures of different light emitting units are arranged separate from one another.

Abstract: Emitter packages and LEDs displays utilizing the packages are disclosed, with the packages providing advantages such as reducing the cost and interconnect complexity for the packages and displays. One emitter package comprises a casing with a plurality of cavities, each cavity having at least one LED. A lead frame structure is included integral to the casing, with the at least one LED from each of the cavities mounted to the lead frame structure. The package is capable of receiving electrical signals for independently controlling the emission from a first and second of the cavities. One LED display utilizes the LED packages mounted in relation to one another to generate a message or image. The LED packages comprise multiple pixels each having at least one LED, with each package capable of receiving electrical signals for independently controlling the emission of at least a first and second of the pixels.

Abstract: A light-emitting device comprises a transparent substrate, an LED die on the transparent substrate, a second substrate on the LED die, and two electrode pins located between the transparent substrate and the second substrate. The LED die comprises a first surface, a second surface opposite to the first surface, and two electrodes located on the first surface, wherein the LED die is enclosed by the transparent substrate and the second substrate, and the two electrodes of the LED die respectively connect to the two electrode pins without a wire bonding process. Each of the two electrode pins comprises a first end and a second end opposite to the first end, and the first end is sandwiched by the LED die and the second substrate, and the second end extends out of the transparent substrate and the second substrate; wherein the first surface comprises a side and the two electrode pins extend in parallel from the side of the LED die toward a same direction away from the side.

Abstract: A method is presented for forming a monolithically integrated semiconductor device. The method includes forming a first device including first hydrogenated silicon-based contacts formed on a first portion of a semiconductor material of an insulating substrate and forming a second device including second hydrogenated silicon-based contacts formed on a second portion of the semiconductor material of the insulating substrate. Source and drain contacts of the first device are formed before a gate contact of the first device and a gate contact of the second device is formed before the emitter and collector contacts of the second device. The first device can be a heterojunction field effect transistor (HJFET) and the second device can be a (heterojunction bipolar transistor) HBT. The HJFET and the HBT are integrated in a neuronal circuit and create negative differential resistance by forming a lambda diode.