Abstract: The present disclosure relates to a display panel, a manufacturing method thereof, and a display device. The display panel comprises a base substrate, a package cover plat disposed to be parallel to the base substrate, a light-emitting layer between the substrate and the package cover plate, and a main package part, which encapsulates a side surface of the base substrate and a side surface of the package cover plate.

Abstract: A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.

Abstract: An organic light emitting device and array substrate are provided. The organic light emitting device includes a light emitting structure layer having a light emitting side and a light extraction layer positioned on the light emitting side of the light emitting structure layer. The light extraction layer includes at least one refractive layer, each of the refractive layers includes a plurality of first light refraction bodies, a plurality of second light refraction bodies, and a polymer layer. In the organic light emitting device and the array substrate of the present invention, light extraction efficiency of the organic light emitting device can be increased by adding the light extraction layer to the organic light emitting structure. Moreover, the structure of the present invention is simple to set up, solving the problems that light extraction is difficult to be realized in prior art and realizing the preparation of a high-efficiency OLED device.

Abstract: To provide a semiconductor device capable of having improved adhesion between a plating film and a wiring layer. A method of manufacturing the semiconductor device includes a step of forming a wiring layer having a surface covered with an oxide film, a step of removing a portion of the oxide film by dry etching to form, in the oxide film, a first opening for exposing a portion of the wiring layer, a step of forming a passivation film covering the wiring layer, is provided with a second opening communicated with the first opening, and is made of an insulating resin material, and a step of growing a plating film on the wiring layer exposed from the first and second openings.

Abstract: A device integrated with a depletion-mode junction field-effect transistor and a method for manufacturing the device. The device includes: a well region, which is of a second conduction type and formed within a first conduction region (214); a JFET source (210), which is of a first conduction type and formed within the well region; a metal electrode (212) of the JFET sources formed on the JFET sources (210), which is in contact with the JFET sources (210); a lateral channel region (208), which is of the first conduction type and formed between two adjacent JFET sources (210), while two ends thereof are in contact with the two adjacent JFET sources (210); and a JFET metal gate (213) formed on the well region.

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

Abstract: An array substrate, a display panel and a display device are disclosed. The array substrate includes a base substrate and a plurality of pixel unit. Each of the pixel unit includes a thin-film-transistor, and the thin-film-transistor includes a gate electrode and a drain electrode; the drain electrode includes a first drain electrode portion, a second drain electrode portion and a first connection portion; and an orthographic projection of the first drain electrode portion on the base substrate and an orthographic projection of the gate electrode on the base substrate are spaced apart, and an orthographic projection of the second drain electrode portion on the base substrate and the orthographic projection of the gate electrode on the base substrate at least partially overlap.

Abstract: A method for directly bonding semiconductor devices from multiple carrier substrates to a target substrate using relative alignments of semiconductor contacts to substrate contacts, as well as relative heights of semiconductor contacts to substrate contacts. The method may include directly bonding a subset of semiconductor devices on a first carrier substrate with a first alignment to a subset of substrate contacts, and directly bonding a subset of second semiconductor device on a second carrier substrate with a second alignment to a subset of substrate contacts. The method may include directly bonding a subset of semiconductor devices with a first height on a first carrier substrate to a first subset of substrate contacts, followed by directly bonding a second subset of second semiconductor devices with a second height on a second carrier substrate to a second subset of substrate contacts.

Abstract: A display device according to an exemplary embodiment includes a display panel including a display area and a non-display area and a polarizing layer disposed on the display panel, and including a main portion for at least covering the display area and an extension for covering part of the non-display area. The polarizing layer includes a groove for extending along a border of the main portion and the extension.

Abstract: A semiconductor device structure includes a region of semiconductor material having an active region and a termination region. An active structure is disposed in the active region and a termination structure is disposed in the termination region. In one embodiment, the termination structure includes a termination trench and a conductive structure within the termination trench and electrically isolated from the region of semiconductor material by a dielectric structure. A dielectric layer is disposed to overlap the termination trench to provide the termination structure as a floating structure. A Schottky contact region is disposed within the active region. A conductive layer is electrically connected to the Schottky contact region and the first conductive layer extends onto a surface of the dielectric layer and laterally overlaps at least a portion of the termination trench.

Abstract: A moisture and hydrogen adsorption getter is provided. The moisture and hydrogen adsorption getter includes a silicon substrate including a concave portion and a convex portion, a silicon oxide layer conformally provided along a surface of the concave portion and a surface of the convex portion and configured to adsorb moisture, and a hydrogen adsorption pattern disposed on the silicon oxide layer. A portion of the silicon oxide layer is exposed between portions of the hydrogen adsorption pattern.

Abstract: A system for pattern-based identification of a driver of a vehicle includes a mobile device; and a server configured to communicate with the mobile device. The mobile device collects movement information during a driving trip via one or more sensors in the mobile device, and communicates the collected movement information to a server. The server analyzes the movement information via a classifier, identifies driving features for the driver based at least in part on the analysis of the movement information, creates an identification model for the driver based on identified driving features, and stores the identification model.

Abstract: Each of subpixels includes: an upper electrode; a lower electrode; an organic light-emitting layer sandwiched between the upper electrode and the lower electrode; and a lower carrier supply layer sandwiched between the lower electrode and the organic light-emitting layer. The lower carrier supply layer is configured to: make contact with the lower electrode and the organic light-emitting layer, respectively; supply carriers from the lower electrode to the organic light-emitting layer; cover the lower electrode entirely in an opening of the pixel defining layer; and have an edge at a top surface of the pixel defining layer surrounding the lower electrode. The organic light-emitting layer covers an entire surface of the lower carrier supply layer including the edge of the lower carrier supply layer.

Abstract: A semiconductor device that includes a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer includes a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of at least two suspended channel structures. The inner spacer may be composed of an n-type or p-type doped glass.

Abstract: A semiconductor device provided in a pixel circuit of a display device includes, in order from a lower side: a substrate; an LTPS layer; a first gate insulating layer; a first metal layer; a first flattened layer; a second gate insulating layer; an oxide semiconductor layer; a second metal layer; a passivation layer; and a third metal layer. The gate electrode layer of an LTPS-TFT and the gate electrode of an oxide semiconductor TFT are formed by the first metal layer.

Abstract: A method of placing light emitting diodes (LEDs) includes embedding an array of LEDs in a polymer layer on a substrate. The method includes detaching at least one LED in the array of LEDs from the substrate by dry-etching the polymer layer in which at least one LED is embedded. A pick-up-tool (PUT) is brought into contact with at least one surface of at least one LED facing away from the substrate, responsive to dry-etching the polymer layer. The PUT is lifted with the at least one LED attached to the PUT.

Abstract: A light-emitting diode (LED) includes: a base having an upward-opening accommodating space; an LED chip disposed at the base, and arranged in the accommodating space; a packaging adhesive covering the LED chip; a lens disposed over the packaging adhesive, wherein: the lens has a first surface proximal to the packaging adhesive; the first surface has: a first subsurface at a center area with a substantially spherical or parabolic shape; a second subsurface with a substantially ring shape and surrounding the first subsurface and extending downward with an increasing diameter; a third subsurface with a substantially ring shape and surrounding the second subsurface, having a top ring edge and extending downward with a decreasing diameter; and a fourth subsurface with a substantially planar shape and surrounding the top ring edge of the third subsurface and connected with the base.

Abstract: A vertical, single column compound semiconductor bipolar junction transistor device includes an all-around extrinsic base. Aspect ratio trapping is employed during fabrication of the transistor device on a silicon substrate. Homojunction and heterojunction devices are formed using III-V materials with appropriate bandgaps. The emitter of the device may be electrically connected by a lateral buried metal contact.

Abstract: Disclosed is a transistor including a substrate, first and second type wells in contact with each other on the substrate; and a breakdown voltage improving region including vertical high concentration doped regions according to first and second types vertically in contact from upper surfaces of the first and second type wells to an upper surface of the substrate in a portion where the first and second type wells are in contact with each other.

Abstract: A electronic device includes an embedded ball land substrate and a semiconductor die. The embedded ball land substrate includes a top surface, a bottom surface opposite the top surface, and one or more side surfaces adjacent the top surface and the bottom surface. The embedded ball land substrate further includes a mold layer on the bottom surface, contact pads on the top surface, and ball lands embedded in the mold layer and electrically connected to the contact pads. The semiconductor die includes a first surface, a second surface opposite the first surface, one or more side surfaces adjacent the first surface and the second surface, and attachment structures along the second surface. The semiconductor die is operatively coupled to the contact pads via the attachment structures.