Abstract: Various embodiments of the present application are directed towards a method for workpiece-level alignment with low alignment error and high throughput. In some embodiments, the method comprises aligning a first alignment mark on a first workpiece to a field of view (FOV) of an imaging device based on feedback from the imaging device, and further aligning a second alignment mark on a second workpiece to the first alignment mark based on feedback from the imaging device. The second workpiece is outside the FOV during the aligning of the first alignment mark. The aligning of the second alignment mark is performed without moving the first alignment mark out of the FOV. Further, the imaging device views the second alignment mark, and further views the first alignment mark through the second workpiece, during the aligning of the second alignment mark. The imaging device may, for example, perform imaging with reflected infrared radiation.

Abstract: A switch device includes: a first electrode; a second electrode opposed to the first electrode; and a switch layer provided between the first electrode and the second electrode, and the switch layer includes one or more kinds of chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S) and one or more kinds of first elements selected from phosphorus (P) and arsenic (As), and further includes one or both of one or more kinds of second elements selected from boron (B) and carbon (C) and one or more kinds of third elements selected from aluminum (Al), gallium (Ga), and indium (In).

Abstract: A method is presented for enabling heat dissipation in resistive random access memory (RRAM) devices. The method includes forming a first thermal conducting layer over a bottom electrode, depositing a metal oxide liner over the first thermal conducting layer, forming a second thermal conducting layer over the metal oxide liner, recessing the second thermal conducting layer to expose the first thermal conducting layer, and forming a top electrode in direct contact with the first and second thermal conducting layers.

Abstract: A device includes a first epitaxial layer, a second epitaxial layer, an interlayer, a gate dielectric layer, and a gate layer. The interlayer is between the first epitaxial layer and the second epitaxial layer. The gate dielectric layer is around the interlayer. The gate layer is around the gate dielectric layer and the interlayer. The interlayer is slanted with respect to a sidewall of the gate layer.

Abstract: Semiconductor devices including bamboo tall via interconnect structures and methods of forming the bamboo tall via interconnect structures generally include a first via in a first dielectric layer including a liner layer and a bulk conductor in the first via, wherein the bulk conductor includes a recess filled with a conductive metal different from the bulk conductor and selected to prevent diffusion of the bulk conductor. At least one additional via is in a second dielectric layer including a liner layer and a bulk conductor in the least one additional via, wherein the second dielectric layer is on the first dielectric layer, and wherein the bulk conductor includes a recess filled with a conductive metal different from the bulk conductor and selected to prevent diffusion of the bulk conductor. The at least one additional via is aligned with the first via.

Abstract: A method for fabricating a semiconductor device includes providing a structure having two fins over a substrate, lower portions of the fins being separated by an isolation structure, a dummy gate structure over the fins, and source/drain features over the fins on both sides of the dummy gate structure; forming a trench in the dummy gate structure between the two fins, where forming the trench removes a portion of the isolation structure; forming a dielectric layer in the trench, where a bottom surface of the dielectric layer extends below a top surface of the isolation structure; and replacing the dummy gate structure with one high-k metal gate structure formed over one of the fins and another high-k metal gate structure formed over the other of the fins.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor substrate. A gate dielectric is disposed over the semiconductor substrate. A first source/drain region and a second source/drain region are disposed in the semiconductor substrate and on opposite sides of the gate dielectric. A gate electrode is disposed over the gate dielectric. A first dishing prevention structure is embedded in the gate electrode, where a perimeter of the first dishing prevention structure is disposed within a perimeter of the gate electrode.

Abstract: A method is presented for constructing high-density static random access memory (SRAM). The method includes forming a nanosheet SRAM by a sidewall image transfer (SIT) process and independently tuning widths of n-type field effect transistor (nFET) nanosheet structures and p-type field effect transistor (pFET) nanosheet structures of the nanosheet SRAM. The nFET nanosheet structures have a first width and the pFET nanosheet structures have a second width, the first width being greater than the second width. A distance between an nFET nanosheet structure and an adjacent pFET nanosheet structure is greater than a distance between two adjacent pFET nanosheet structures.

Abstract: A display device includes a pixel layer for displaying an image and a circuit layer including a thin film transistor for driving the pixel layer. The thin film transistor includes a semiconductor layer including a channel region and a source region and a drain region sandwiching the channel region, a first gate electrode facing the channel region on a first side which is either above or below the semiconductor layer, a second gate electrode facing at least the channel region and the source region on a second side opposite to the first side, a source electrode connected to the source region, and a drain electrode connected to the drain region. The source electrode penetrates through the semiconductor layer and is connected to the second gate electrode on the second side.

Abstract: Various embodiments of the present disclosure are directed towards a resistive random access memory (RRAM) device including a scavenger layer. A bit line overlying a semiconductor substrate. A data storage layer around outer sidewalls and a top surface of the bit line. A word line overlying the data storage layer. A scavenger layer between the word line and the bit line such that a bottom surface of the scavenger layer is aligned with a bottom surface of the bit line. A lateral thickness of the scavenger layer is less than a vertical thickness of the scavenger layer.

Abstract: A passivated semiconductor device structure includes a III-nitride structure and a passivation layer. The III-nitride structure includes a high electron mobility transistor (HEMT). The passivation layer includes a dielectric, which is formed over the structure to provide passivation and forms an interface with the structure. The interface provides a transition between the structure and the dielectric having a thickness of at least two atomic layers. The interface also has a characteristic density of interface states less than a reference density of interface states that corresponds to a thickness of at most one atomic layer. The transition, which constitutes a rough interface, allows a relatively low density of interface states, and thus improves high-frequency performance of the device structure.

Abstract: A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure.

Abstract: A gallium nitride (GaN) transistor which includes multiple insulator semiconductor interface regions. Two or more first insulator segments and two or more second insulator segments are positioned between the gate and drain contacts and interleaved together. At least one first insulator segment is nearer to the gate contact than the second insulator segments. At least one second insulator segment is nearer to the drain contact than the first insulator segments. The first and second insulators are chosen such that a net electron donor density above the channel under the first insulator segments is lower than a net electron density above the channel under the second insulator segments. The first insulator segments reduce gate leakage and electric fields near the gate that cause high gate-drain charge. The second insulator segments reduce electric fields near the drain contact and provide a high density of charge in the channel for reduced on-resistance.

Abstract: A semiconductor arrangement includes a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement includes a second semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The second semiconductor column is separated a first distance from the first semiconductor column along a first axis. The semiconductor arrangement includes a third semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The third semiconductor column is separated a second distance from the first semiconductor column along a second axis that is substantially perpendicular to the first axis. The second distance is different than the first distance.

Abstract: Provided is a LED device and a backlight module. The LED device comprises a bracket, a LED chip and an encapsulation layer. A reflective cup is arranged on the bracket, and the LED chip is arranged in the reflective cup. The encapsulation layer encases and encapsulates the LED chip in the reflective cup, the encapsulation layer has a top surface of the encapsulation layer. The top surface of the encapsulation layer is located above a top surface of the reflective cup, and is a lens curved surface. In an on-state, the LED device has virtual cross sections passing through a geometrical center of the LED chip and perpendicular to a top surface of the bracket, in at least one of the virtual cross sections of the LED device, the LED device has luminous efficiency greater than or equal to 95% within a beam angle of at least 60°.

Abstract: A display component and a display device are provided. The display component includes a display panel including a first substrate, a thin-film transistor array layer, a second substrate and a coil-containing film layer. The coil-containing film layer at least includes a first metal layer, a first insulation layer, a second metal layer, and a second insulation layer. The first metal layer includes at least one first coil and the second metal layer includes at least one signal line, where the one first coil of the first metal layer is electrically connected to one or two signal lines of the second metal layer. An orthographic projection of the first coil on the first substrate is at least partially in the display region. The display component further includes a coil drive circuit, where the coil drive circuit is electrically connected to each of the first coil and the signal line, respectively.

Abstract: A system and method of providing a coil in an electronic communication device in is disclosed. Multiple dielectric layers are deposited and patterned on a semiconductor substrate or insulating mold compound. The dielectric layers provide conductive contact with a contact pad on the underlying structure. Shielding for the coil, including a seed layer covered by an insulating material, is disposed in a via of a lowermost of the dielectric layers. Grounding of the shielding seed layer is through a contact pad on the substrate or a trace between the dielectric layers. A coil is fabricated over the shielding and a solder mask deposited and patterned to cover and insulate the coil. The coil is fabricated in a via of a dielectric layer immediately below the solder mask or above this dielectric layer. Electrical contact is provided by multiple copper and seed layers in the solder mask and dielectric layers.

Abstract: A substrate with a (001) orientation is provided. A gallium arsenide (GaAs) layer is epitaxially grown on the substrate. The GaAs layer has a reconstruction surface that is a 4×6 reconstruction surface, a 2×4 reconstruction surface, a 3×2 reconstruction surface, a 2×1 reconstruction surface, or a 4×4 reconstruction surface. Via an atomic layer deposition process, a single-crystal structure yttrium oxide (Y2O3) layer is formed on the reconstruction surface of the GaAs layer. The atomic layer deposition process includes water or ozone gas as an oxygen source precursor and a cyclopentadienyl-type compound as an yttrium source precursor.

Abstract: A display device includes a sensing line and a data driver. The sensing line is in a display panel. The data driver includes a plurality of integrated circuits. Each of the integrated circuits includes an interface, which includes a mobile industry processor interface (MIPI) and a crack detector. The crack detector detects cracks of the panel based on the sensing line and transmits and receives information corresponding to the crack to and from adjacent ones of the integrated circuits using a transmission terminal and a reception terminal in the MIPI.

Abstract: A multispectral image sensor includes a semiconductor layer and a number of pixels formed inside and on top of the semiconductor layer. The pixels include a first pixel of a first type formed inside and on top of a first portion of the semiconductor layer and a second pixel of a second type formed inside and on top of a second portion of the semiconductor layer. The first pixel has a first thickness that defines a vertical cavity resonating at a first wavelength and the second pixel has a second thickness different from the first thickness. The second thickness defines a vertical cavity resonating at a second wavelength different than the first wavelength.