Patents Examined by Erica Smith-Hicks
  • Patent number: 6251248
    Abstract: A microfabrication process for making a microstructure product comprises: micromachining a polymer substrate for forming a three-dimensional microstructure pattern with deep cavities; shrinking and minimizing the diameter or width of each cavity of the microstructure pattern by steadily swelling the polymer, which is prefixed on a cathode of an electroforming system, by saturating the electrolyte solution into the polymer; electroforming in the electroforming system electrically connected with an anode and the cathode for filling metal in the cavities in the polymer; and desorption of the electrolyte from the polymer to shrink the polymer to be separated from an electroformed microstructure product, and demolding for obtaining the microstructure product having a high aspect ratio of 100 or even higher. The diameter or width of each cavity is shrunk to be smaller, thereby increasing the aspect ratio of the microstructure product.
    Type: Grant
    Filed: October 15, 1999
    Date of Patent: June 26, 2001
    Inventor: Ching-Bin Lin
  • Patent number: 6241870
    Abstract: The specification describes novel rhodium sulfate complex solutions which have a minimum of metal to metal complexing and are mostly complexed through the sulfate groups. Use of these solutions as electrolytes for plating rhodium results in electroplated layers with improved brightness and reduced stress.
    Type: Grant
    Filed: May 6, 1999
    Date of Patent: June 5, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: Joseph Anthony Abys, Conor Anthony Dullaghan, Peter Epstein, Joseph John Maisano, Jr.
  • Patent number: 6241868
    Abstract: A method for electroplating a film onto a substrate. Electrical power is supplied to the plating surface through electrical contact made to contact pads on the underside of the substrate. Contact to the contact pads is made within a liquid-tight region. The contact pads are connected to the plating surface through the substrate. Because the contact scheme is provided within a liquid-tight region on the underside of the substrate, the contacts do not erode or become plated, nor do they consume an area of the plating surface.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: June 5, 2001
    Assignee: International Business Machines Corporation
    Inventors: Glen N. Biggs, Donald M. Brewer, James E. Fluegel, Suryanarayana Kaja, Ashwani K. Malhotra, Phillip W. Palmatier
  • Patent number: 6238529
    Abstract: The apparatus for electrolytically treating printed circuit boards 3, through which apparatus the printed circuit boards are continuously guidable in a plane of conveyance in a substantially horizontal direction of conveyance, has the following features: Counter-electrodes 1,2 are disposed opposite the plane of conveyance and substantially parallel thereto on at least one side, so that electrolytic chambers 4,5 are formed between counter-electrodes, which are situated opposite one another, or between the counter-electrodes and the plane of conveyance, the counter-electrodes forming respective substantially continuous electrode faces. Guide elements 7,8 for the printed circuit boards are disposed in the electrolytic chamber. Contact elements 11 are provided for the electrical contacting of the printed circuit boards. Electrolyte spraying arrangements 13 are also provided for conveying the electrolytic fluid towards the surfaces of the printed circuit boards. Openings are provided in the counter-electrodes.
    Type: Grant
    Filed: November 22, 1999
    Date of Patent: May 29, 2001
    Assignee: Atotech Deutschland GmbH
    Inventors: Jens Geissler, Thomas Rydlewski, Lorenz Kopp, Ralf-Peter Wächter, Reinhard Schneider
  • Patent number: 6235179
    Abstract: An electroplated structure for a field emission display device and method for forming an electroplated structure for a field emission display device. In one embodiment, the present invention forms a molded structure over selected portions of a flat panel display device. Next, the present embodiment deposits an electroplating seed layer over the molded structure. After the deposition of the electroplating seed layer, the present embodiment electroplates material onto portions of the electroplating seed layer such that an electroplated structure is formed at desired regions of the flat panel display device. In such an embodiment, the present invention provides an electroplated structure which contains substantially no polyimide material. As a result, the present embodiment eliminates the cost and production of outgassed contaminants associated with prior art structures.
    Type: Grant
    Filed: May 12, 1999
    Date of Patent: May 22, 2001
    Assignee: Candescent Technologies Corporation
    Inventors: Ronald S. Besser, Robert M. Duboc, Jr.
  • Patent number: 6235177
    Abstract: A method for forming an aperture plate comprises providing a mandrel that is constructed of a mandrel body having a conductive surface and a plurality of non-conductive islands disposed on the conductive surface. The mandrel is placed within a solution containing a material that is to be deposited onto the mandrel. Electrical current is applied to the mandrel to form an aperture plate on the mandrel, with the apertures having an exit angle that is in the range from about 30° to about 60°.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: May 22, 2001
    Assignee: Aerogen, Inc.
    Inventors: Scott Borland, Gary Baker
  • Patent number: 6228520
    Abstract: A composition which is densifiable at low temperatures in an air atmosphere suitable for use as an interconnect layer in a solid oxide fuel cell. Binary alloying of SrO and CaO with LaCrO3 is used to form a compound having the general formula La(1−x)(Sr,Ca)xCrO3 which is a stabilized form of LaCrO3 and has the desirable properties for a fuel cell interconnect layer.
    Type: Grant
    Filed: April 10, 1997
    Date of Patent: May 8, 2001
    Assignee: The Dow Chemical Company
    Inventor: Yi-Hung Chiao
  • Patent number: 6224737
    Abstract: A semiconductor structure having a trench formed therein is provided. The semiconductor structure may be a substrate with an overlying interlevel metal dielectric layer having the trench. A voltage is applied to the trenched semiconductor inducing a bias field where there is a first field proximate the trench bottom and a second field, greater than the first field, proximate the trench's upper side walls and the semiconductor upper surface proximate the trench. The semiconductor structure is placed into an electroplating solution containing a predetermined concentration of brighteners and levelers. Because of the induced bias field, the brightener concentration is greater proximate the trench bottom and the leveler concentration is greater the trench's upper side walls and the semiconductor upper surface proximate the trench.
    Type: Grant
    Filed: August 19, 1999
    Date of Patent: May 1, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ming-Hsing Tsai, Wen-Jye Tsai, Shau-Lin Shue, Chen-Hua Yu
  • Patent number: 6221228
    Abstract: A part fabricating method comprises the steps of machining an object to fabricate a part cast mold, depositing a first metal on a surface of the cast mold to form a first metal layer, and depositing a second metal different in kind from the first metal inside the cast mold to form a part. The first metal layer is then selectively removed to take out the part formed inside the cast mold.
    Type: Grant
    Filed: December 2, 1998
    Date of Patent: April 24, 2001
    Assignee: Seiko Instruments Inc.
    Inventors: Reiko Irie, Masayuki Suda, Toshihiko Sakuhara, Tatsuaki Ataka
  • Patent number: 6221227
    Abstract: A microfabrication process comprises the swelling of at least a hydrophilic polymer in order for shrinking each cavity size of a micromachined microstructure pattern from three-dimensional orientations, whereby upon filling or deposition of metal into each cavity of the pattern when performing an electroforming step, a supermini microstructure with slim, fine, thin and small size can be obtained as geometrically miniaturized from three-dimensional orientations.
    Type: Grant
    Filed: November 2, 1999
    Date of Patent: April 24, 2001
    Inventors: Ching-Bin Lin, Shung-Wen Kang, Mau-Kuo Wei
  • Patent number: 6221230
    Abstract: A method and apparatus for forming a layer of plating on a base material and a method for manufacturing a three dimensional object. The plating apparatus includes a nozzle for delivering a stream of plating fluid and an electric source for applying a voltage between the base material and the nozzle. The nozzle has an outer wall and a stem located at its center. The nozzle delivers plating fluid from the opening of the nozzle in an annular manner to produce a stream that has a substantially uniform flow velocity when the stream hits the base material. In an another embodiment, the nozzle has surrounding conduit for conducting air. The air increases the velocity of a peripheral portion of the stream. To manufacture a three dimensional object, a plating layer is deposited, and the nozzle is moved to form a desired shape while piling the layer.
    Type: Grant
    Filed: May 14, 1998
    Date of Patent: April 24, 2001
    Inventors: Hiromitsu Takeuchi, Masahiro Okumiya, Yoshiki Tsunekawa, Yutaka Kawai
  • Patent number: 6217727
    Abstract: An electroplating apparatus is provided with a metal target and a device for supporting a semiconductor wafer (or other workpiece) in an electroplating solution. The target (anode) may be located relatively far from the wafer surface (cathode) at the beginning of the plating process, until a sufficient amount of metal is plated. When an initial amount of metal is built up on the wafer surface, the target may be moved closer to the wafer for faster processing. The movement of the target may be controlled automatically according to one or more process parameters.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: April 17, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Scott E. Moore
  • Patent number: 6218031
    Abstract: An anticorrosive film which can be formed without causing any substantial environmental pollution, can effectively prevent any corrosion from occurring through pinholes in a corrosive environment, allows the formation of a contact of high reliability maintaining a low contact resistance, and remains stable for a long time on the surface of a substrate having a gold or gold alloy layer without causing any variation in contact resistance, or undergoing any change in outward appearance. The film is formed by bringing the substrate surface into contact with an aqueous solution containing at least one of mercaptobenzothiazole and its derivatives as represented by the following formula at a concentration of 6 to 30 mmol/l.
    Type: Grant
    Filed: June 28, 1999
    Date of Patent: April 17, 2001
    Assignee: Japan Aviation Electronics Industry, Ltd.
    Inventors: Tadashi Shintani, Yasuhiro Yuzurihara
  • Patent number: 6217736
    Abstract: The apparatus according to the invention is used for electrolytically treating a board-shaped substrate to be treated, preferably printed circuit boards, in a continuous system, through which the item to be treated is guidable in a plane of conveyance in a substantially horizontal direction of conveyance, the apparatus having counter-electrodes (2), which are situated substantially parallel to one another opposite the plane of conveyance, and screens (11) for shielding from high current density fields in the edge region of the item to be treated (1), said screens being disposed between the plane of conveyance and the counter-electrodes, the screens each being in the form of at least two flat portions (12,13), which are disposed substantially parallel to each other, one portion (13) of the screens being disposed so as to lie opposite the plane of conveyance, and the other portion (12) being disposed so as to lie opposite the counter-electrodes, and the screens being mounted so as to be displaceable in a direct
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: April 17, 2001
    Assignee: Atotech Deutschland GmbH
    Inventors: Lorenz Kopp, Wolfang Plöse, Ralf-Peter Wachter
  • Patent number: 6214193
    Abstract: A plating cell has an inner plating bath container for performing electroplating on a work piece (e.g., a wafer) submerged in a solution contained by the inner plating bath container. A reclaim inlet funnels any solution overflowing the inner plating bath container back into a reservoir container to be circulated back into the inner plating bath container. A waste channel is also provided having an inlet at a different height than the inlet of the reclaim channel. After electroplating, the wafer is lifted to a position and spun. While spinning, the wafer is thoroughly rinse with, for example, ultra pure water. The spin rate and height of the wafer determine whether the water and solution are reclaimed through the reclaim channel or disposed through the waste channel.
    Type: Grant
    Filed: August 13, 1999
    Date of Patent: April 10, 2001
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Steven W. Taatjes, Robert J. Contolini, Evan E. Patton
  • Patent number: 6214180
    Abstract: A method, system and structure for a pin grid or pad grid array structure includes a plurality of pins connected to an electronic structure, a power plane within the electronic structure electrically connected to power pins, a ground plane within the electronic structure, and fuse portions electrically connecting the ground plane to ground pins and signal pins. The power plane and the ground plane create a charge in the pins during electroplating of the pins. The fuse portions disconnecting the signal pins from the ground plane after the electroplating.
    Type: Grant
    Filed: February 25, 1999
    Date of Patent: April 10, 2001
    Assignee: International Business Machines Corporation
    Inventors: Arden S. Lake, Emanuele F. Lopergolo, Joseph M. Sullivan
  • Patent number: 6214192
    Abstract: A method for forming an ink jet nozzle plate with ink jet nozzles, including providing a first mold formed with spaced-apart recesses; providing inlay material in the spaced-apart recesses; attaching a base to the inlay material; separating the first mold from the inlay material and the base, thereby forming a final mold having a plurality of inlay material protrusions over the base, the protrusions and base defining the shape and the size of the ink jet nozzles; providing plate forming material between the protrusions and over the base in the final mold; and releasing the plate forming material to form an ink jet nozzle plate having a plurality of ink jet nozzles.
    Type: Grant
    Filed: December 10, 1998
    Date of Patent: April 10, 2001
    Assignee: Eastman Kodak Company
    Inventors: Gilbert A. Hawkins, Xin Wen
  • Patent number: 6210554
    Abstract: A method of plating which improves the uniformity of a plated coating thickness without changing the flow velocity of a feed plating solution. An aperture at a center of a mesh anode electrode of a plating apparatus produces an electric field density distribution between the mesh anode electrode and a wafer that is lower in the central portion of the wafer than at the edge portion of the wafer.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: April 3, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuya Kosaki, Masahiro Tamaki
  • Patent number: 6193860
    Abstract: An apparatus for optimizing electrical currents to improve copper plating uniformity on a semiconductor wafer is disclosed. The use of multiple anodes of the embodiment provides for variable electrical currents to the semiconductor wafer, the variable feature of the variable electrical currents compensating for non-uniform electroplating characteristics.
    Type: Grant
    Filed: April 23, 1999
    Date of Patent: February 27, 2001
    Assignee: VLSI Technolgy, Inc.
    Inventor: Milind Weling
  • Patent number: 6193870
    Abstract: A process for fabricating a nanofilament field emission device in which a via in a dielectric layer is self-aligned to gate metal via structure located on top of the dielectric layer. By the use of a hard mask layer located on top of the gate metal layer, inert to the etch chemistry for the gate metal layer, and in which a via is formed by the pattern from etched nuclear tracks in a trackable material, a via is formed by the hard mask will eliminate any erosion of the gate metal layer during the dielectric via etch. Also, the hard mask layer will protect the gate metal layer while the gate structure is etched back from the edge of the dielectric via, if such is desired. This method provides more tolerance for the electroplating of a nanofilament in the dielectric via and sharpening of the nanofilament.
    Type: Grant
    Filed: May 1, 1997
    Date of Patent: February 27, 2001
    Assignee: The Regents of the University of California
    Inventors: Jeffrey D. Morse, Robert J. Contolini