Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.

Abstract: The present invention is provided to improve quality or manufacturing throughput of a semiconductor device. A method includes supplying a source gas to a substrate in a process chamber; exhausting an inside of the process chamber; supplying a reaction gas to the substrate; and exhausting the inside of the process chamber, wherein the source gas and/or the reaction gas is supplied in temporally separated pulses in the supply of the source gas and/or in the supply of the reaction gas. Then, the source gas and/or the reaction gas is supplied in temporally separated pulses to form a film during a gas supply time determined by a concentration distribution of by-products formed on a surface of the substrate.

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon, a first hard mask atop the gate structure, and an interlayer dielectric (ILD) layer around the gate structure and the first hard mask; removing part of the first hard mask; forming a second hard mask layer on the first hard mask and the ILD layer; and planarizing part of the second hard mask layer to form a second hard mask on the first hard mask.

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.

Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a clamping electrode for electrostatically clamping the work piece to the work piece support; providing a mechanical partition between the plasma source and the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.

Abstract: An ink of the formula: 60-80% by weight BaTiO3 particles coated with SiO2; 5-50% by weight high dielectric constant glass; 0.1-5% by weight surfactant; 5-25% by weight solvent; and 5-25% weight organic vehicle. Also a method of manufacturing a capacitor comprising the steps of: heating particles of BaTiO3 for a special heating cycle, under a mixture of 70-96% by volume N2 and 4-30% by volume H2 gas; depositing a film of SiO2 over the particles; mechanically separating the particles; incorporating them into the above described ink formulation; depositing the ink on a substrate; and heating at 850-900° C. for less than 5 minutes and allowing the ink and substrate to cool to ambient in N2 atmosphere. Also a dielectric made by: heating particles of BaTiO3 for a special heating cycle, under a mixture of 70-96% by volume N2 and 4-30% by volume H2 gas; depositing a film of SiO2 over the particles; mechanically separating the particles; forming them into a layer; and heating at 850-900° C.

Abstract: A package wafer processing method includes a processing step of processing a package wafer along planned dividing lines by a laser beam irradiation unit and forming processing grooves in the package wafer. The processing step includes detecting a processing groove and an exposed key pattern closest to the planned dividing line corresponding to the processing groove at a predetermined timing and measuring, as a deviation amount, the difference between the distance from the processing groove to the exposed key pattern and the distance that is registered in a registration step and is from the planned dividing line corresponding to the processing groove to the closest key pattern. An indexing feed mechanism is corrected according to the deviation amount.

Abstract: Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided three-dimensional (3D) hierarchal architecture scheme for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring. In an embodiment a first word line architecture may be formed on a front side of an IC chip and connected to a second word line architecture formed on a back side of the IC chip through intra-wafer, TSVs, thereby relocating required wiring to the back side of the IC chip.

Abstract: The semiconductor device includes a stacked structure having alternately stacked conductive patterns and interlayer insulating patterns, a through-hole passing through the stacked structure, a channel pattern formed in the through-hole and protruding from an inside of the through hole over the through-hole, and a capping conductive pattern formed to be in contact with the protruded channel pattern and have a width greater than the through-hole.

Abstract: A fabricating method of an anti-fuse structure, comprising: providing a substrate having a first conductive plug and a second conductive plug separated from the first conductive plug; forming an amorphous silicon layer on the substrate, wherein a portion of the amorphous silicon layer overlapping the first conductive plug is defined as a first region, and a portion of the amorphous silicon layer overlapping the second conductive plug is defined as a second region; performing an implantation process to the first region and the second region, wherein the first region has a higher doping concentration than the second region; forming a titanium nitride layer on the amorphous silicon layer; and patterning the titanium nitride layer and the amorphous silicon layer.

Abstract: A light emitting diode (LED) device and packaging for same is disclosed. In some aspects, the LED is manufactured using a vertical configuration including a plurality of layers. Certain layers act to promote mechanical, electrical, thermal, or optical characteristics of the device. The device avoids design problems, including manufacturing complexities, costs and heat dissipation problems found in conventional LED devices. Some embodiments include a plurality of optically permissive layers, including an optically permissive cover substrate or wafer stacked over a semiconductor LED and positioned using one or more alignment markers.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a fin structure formed over the substrate. The semiconductor structure further includes an isolation structure formed around the fin structure and a gate structure formed across the fin structure. In addition, the gate structure includes a first portion formed over the fin structure and a second portion formed over the isolation structure, and the second portion of the gate structure includes an extending portion extending into the isolation structure.

Abstract: Methods for processing of a workpiece are disclosed. A fluid that contains a desired dopant is prepared. The workpiece is immersed in this fluid, such that the dopant is able to contact all surfaces of the workpiece. The fluid is then evacuated, leaving behind the dopant on the workpiece. The dopant is then subjected to a thermal treatment to drive the dopant into the surfaces of the workpiece. In certain embodiments, a selective doping process may be performed by applying a mask to certain surfaces prior to immersing the workpiece in the fluid. In certain embodiments, the fluid may be in a super-critical state to maximize the contact between the dopant and the workpiece.

Abstract: Provided are an oxide semiconductor layer in which the number of defects is reduced and a highly reliable semiconductor device including the oxide semiconductor. A first oxide semiconductor layer having a crystal part is formed over a substrate by a sputtering method. A second oxide semiconductor layer is formed by a thermal chemical vapor deposition method over the first oxide semiconductor layer. The second oxide semiconductor layer is formed by epitaxial growth using the first oxide semiconductor layer as a seed crystal. A channel is formed in the second oxide semiconductor layer.

Abstract: An apparatus and a method for determining the temperature of a substrate, in particular of a semiconductor substrate during the heating thereof by means of at least one first radiation source are disclosed. A determination of the temperature is based on detecting first and second radiations, each comprising radiation emitted by the substrate due to its own temperature and radiation emitted by the first radiation, which is reflected at the substrate and at least one of a drive power of the first radiation source and the radiation intensity of the first radiation source.

Abstract: A method of forming capacitors includes providing first capacitor electrodes within support material. The first capacitor electrodes contain TiN and the support material contains polysilicon. The polysilicon-containing support material is dry isotropically etched selectively relative to the TiN-containing first capacitor electrodes using a sulfur and fluorine-containing etching chemistry. A capacitor dielectric is formed over sidewalls of the first capacitor electrodes and a second capacitor electrode is formed over the capacitor dielectric. Additional methods are disclosed.

Abstract: Disclosed are structures and methods of forming the structures so as to have a photodetector isolated from a substrate by stacked trench isolation regions. In one structure, a first trench isolation region is in and at the top surface of a substrate and a second trench isolation region is in the substrate below the first. A photodetector is on the substrate aligned above the first and second trench isolation regions. In another structure, a semiconductor layer is on an insulator layer and laterally surrounded by a first trench isolation region. A second trench isolation region is in and at the top surface of a substrate below the insulator layer and first trench isolation region. A photodetector is on the semiconductor layer and extends laterally onto the first trench isolation region. The stacked trench isolation regions provide sufficient isolation below the photodetector to allow for direct coupling with an off-chip optical fiber.

Abstract: Wafer alignment with restricted visual access has been disclosed. In an example, a method of processing a substrate for fabricating a solar cell involves supporting the substrate over a stage. The method involves forming a substantially opaque layer over the substrate. The substantially opaque layer at least partially covers edges of the substrate. The method involves performing fit-up of the substantially opaque layer to the substrate. The method involves illuminating the covered edges of the substrate with light transmitted through the stage, and capturing a first image of the covered edges of the substrate based on the light transmitted through the stage. The method further includes determining a first position of the substrate relative to the stage based on the first image of the covered edges. The substrate may be further processed based on the determined first position of the substrate under the substantially opaque layer.