Abstract: A method of manufacturing a semiconductor structure, by depositing a dielectric layer is a dummy gate, or an existing gate structure, prior to the formation of gate spacers. Following the formation of spacers, and in some embodiments replacing a dummy gate with a final gate structure, oxygen is introduced to a gate dielectric through a diffusion process, using the deposited dielectric layer as a diffusion pathway.

Abstract: An array of semiconductor fins is formed on a top surface of a substrate. A dielectric material liner is formed on the surfaces of the array of semiconductor fins. A photoresist layer is applied and patterned such that sidewalls of an opening in the photoresist layer are parallel to the lengthwise direction of the semiconductor fins, and are asymmetrically laterally offset from a lengthwise direction passing through the center of mass of a semiconductor fin to be subsequently removed. An angled ion implantation is performed to convert a top portion of dielectric material liner into a compound material portion. The compound material portion is removed selective to the remaining dielectric material liner, and the physically exposed semiconductor fin can be removed by an etch or converted into a dielectric material portion by a conversion process. The dielectric material liner can be removed after removal of the semiconductor fin.

Abstract: An apparatus comprises a nanowire having a channel region, a gate structure surrounding a lower portion of the channel region, wherein the gate structure comprises a first dielectric layer comprising a vertical portion and a horizontal portion, a first workfunction metal layer over the first dielectric layer comprising a vertical portion and a horizontal portion and a low-resistivity metal layer over the first workfunction metal layer, wherein an edge of the low-resistivity metal layer and an edge of the vertical portion of the first workfunction metal layer are separated by a dielectric region and the low-resistivity metal layer is electrically coupled to the vertical portion of the first workfunction metal layer through the horizontal portion of the first workfunction metal layer.

Abstract: Systems and methods for forming solar cells with CuInSe2 and Cu(In,Ga)Se2 films are provided. In one embodiment, a method comprises: during a first stage (220), performing a mass transport through vapor transport of an indium chloride (InClx) vapor (143, 223) and Se vapor (121, 225) to deposit a semiconductor film (212, 232, 252) upon a substrate (114, 210, 230, 250); heating the substrate (114, 210, 230, 250) and the semiconductor film to a desired temperature (112); during a second stage (240) following the first stage (220), performing a mass transport through vapor transport of a copper chloride (CuClx) vapor (143, 243) and Se vapor (121, 245) to the semiconductor film (212, 232, 252); and during a third stage (260) following the second stage (240), performing a mass transport through vapor transport of an indium chloride (InClx) vapor (143, 263) and Se vapor (121, 265) to the semiconductor film (212, 232, 252).

Abstract: A substrate carrier arrangement (10, 11) for a coating system (12) is provided, comprising a carrier (1) which comprises at least one support region (3) having a support surface (30), on which a substrate support (2) is arranged, and which support region comprises in the support surface (30) at least one first and one second gas inlet (4, 5), wherein the first gas inlet (4) is at a smaller distance from a center (M) of the support surface (30) than the second gas inlet (5) and wherein the first and second gas inlet (4, 5) comprise mutually independent gas feeds (40, 50) which are arranged to supply gases having mutually different thermal conductivities. A coating system comprising a substrate carrier arrangement and a method for performing a coating process are also provided.

Abstract: Described herein are semiconductor devices and methods of forming the same. In some aspects, methods of forming a semiconductor device includes forming a gate stack having a self-aligning cap and a gate metal on a substrate, depositing a resist mask onto the semiconductor device, and patterning the resist mask such that the gate stack is exposed. Additionally, methods include removing the self-aligning cap and the gate metal from the exposed gate stack, depositing a resistor metal on the semiconductor device such that a metal resistor is formed within the exposed gate stack, and forming a bar contact and contact via above the metal resistor.

Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.

Abstract: Methods for doping an absorbent layer of a p-n heterojunction in a thin film photovoltaic device are provided. The method can include depositing a window layer on a transparent substrate, where the window layer includes at least one dopant (e.g., copper). A p-n heterojunction can be formed on the window layer, with the p-n heterojunction including a photovoltaic material (e.g., cadmium telluride) in an absorber layer. The dopant can then be diffused from the window layer into the absorber layer (e.g., via annealing).

Abstract: A semiconductor light-emitting element includes a first semiconductor layer of a first conductive type, a second semiconductor layer of a second conductive type, a light-emitting layer formed between the first semiconductor layer and the second semiconductor layer, a first electrode connected to the first semiconductor layer, and a second electrode connected to the second semiconductor layer. The second electrode includes an ohmic electrode contacting the second semiconductor layer, and a semiconductor electrode made of a semiconductor layer contacting the ohmic electrode.

Abstract: A silicon carbide substrate including a first layer having first conductivity type, a second layer having second conductivity type, and a third layer having the first conductivity type is formed. A trench provided with an inner surface having a side wall surface and a bottom surface is formed, the side wall surface extending through the third layer and the second layer and reaching the first layer, the bottom surface being formed of the first layer. A silicon film is formed to cover the bottom surface. A gate oxide film is formed on the inner surface by oxidation in the trench. The gate oxide film includes a first portion formed by oxidation of the silicon carbide substrate, and a second portion formed by oxidation of the silicon film on the bottom surface. Accordingly, a method for manufacturing a silicon carbide semiconductor device having a high breakdown voltage is provided.

Abstract: The inventions relates to a method of manufacturing a circuit incorporating a solid state light emitting component, the method including providing an insulating layer, producing at least one through hole in the insulating layer, providing a conductive layer, bonding a main surface of the conductive layer to the insulating layer, and positioning at least one solid state light emitting component in the hole of the insulating layer and connecting this component to the conductive layer.

Abstract: Semiconductor devices and methods are provided for integrally forming electromechanical devices (e.g. MEMS or NEMS devices) with CMOS devices in a FEOL (front-end-of-line) structure as part of a replacement metal gate process flow. For example, a method includes forming an electromechanical device in a first device region of a substrate and forming a transistor device in a second device region of the substrate. The electromechanical device includes a sacrificial anchor structure and a sacrificial cantilever structure formed of a sacrificial material. The transistor device includes a sacrificial gate electrode structure formed of the sacrificial material. A replacement metal gate process is performed to replace the sacrificial gate electrode structure of the transistor device with a metallic gate electrode, and to replace the sacrificial anchor structure and the sacrificial cantilever structure with a metallic anchor structure and a metallic cantilever structure.

Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a clamping electrode for electrostatically clamping the work piece to the work piece support; providing a mechanical partition between the plasma source and the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.

Abstract: Methods of annealing a thin semiconductor wafer are disclosed. The methods allow for high-temperature annealing of one side of a thin semiconductor wafer without damaging or overheating heat-sensitive electronic device features that are either on the other side of the wafer or embedded within the wafer. The annealing is performed at a temperature below the melting point of the wafer so that no significant dopant redistribution occurs during the annealing process. The methods can be applied to activating dopants or to forming ohmic contacts.

Abstract: A method for manufacturing a three-dimensional resistive memory array is disclosed. The method comprises forming a repetitive sequence comprising an isolating layer, a semiconductor layer, a gate insulating layer, and a conductive layer. By performing a plurality of processing steps on the repetitive sequence a three-dimensional resistive memory array is obtained. A three-dimensional resistive memory array is further disclosed.

Abstract: The present disclosure provides a deep trench capacitor device. A first capacitor electrode is made up of a doped region of semiconductor substrate in which two or more trenches are arranged. A second capacitor electrode is made up of a continuous body of conductive material. The continuous body of conductive material includes a lower body portion filling the two or more trenches and an upper body portion extending continuously over the lower body portion. The upper body portion extends upwardly out of the trenches by a non-zero distance. A capacitor dielectric liner is arranged in the two or more trenches to separate the first and second capacitor electrodes. The capacitor dielectric liner extends continuously out of the two or more trenches along outer sidewalls of the upper body portion.

Abstract: Disclosed are structures and methods of forming the structures so as to have a photodetector isolated from a substrate by stacked trench isolation regions. In one structure, a first trench isolation region is in and at the top surface of a substrate and a second trench isolation region is in the substrate below the first. A photodetector is on the substrate aligned above the first and second trench isolation regions. In another structure, a semiconductor layer is on an insulator layer and laterally surrounded by a first trench isolation region. A second trench isolation region is in and at the top surface of a substrate below the insulator layer and first trench isolation region. A photodetector is on the semiconductor layer and extends laterally onto the first trench isolation region. The stacked trench isolation regions provide sufficient isolation below the photodetector to allow for direct coupling with an off-chip optical fiber.

Abstract: A method of forming an interdigitated back contact solar cell is described. The method uses a deposition process to create a doped glass layer on the substrate, which, when diffused, created either the emitter or back surface fields. The deposition process may also create an oxide layer on top of the doped glass layer. This oxide layer serves as a mask for a subsequent ion implant. This ion implant directs ions having the opposite conductivity of the doped glass layer into exposed regions of the substrate. A thermal process is used to diffuse the dopant from the doped glass layer into the substrate and repair any damage caused by the ion implant.

Abstract: A thin-film deposition mask includes a mask body, the mask body having a first surface and a second surface that is an opposite surface of the first surface, the mask body having a plurality of deposition holes therein, and a spacer near the deposition holes, the spacer protruding from the first surface of the mask body in a vertical direction.

Abstract: A semiconductor device is disclosed. One embodiment includes a lateral HEMT (High Electron Mobility Transistor) structure with a heterojunction between two differing group III-nitride semiconductor compounds and a layer arranged on the heterojunction. The layer includes a group III-nitride semiconductor compound and at least one barrier to hinder current flow in the layer.