Abstract: A light emitting diode (LED) device and packaging for same is disclosed. In some aspects, the LED is manufactured using a vertical configuration including a plurality of layers. Certain layers act to promote mechanical, electrical, thermal, or optical characteristics of the device. The device avoids design problems, including manufacturing complexities, costs and heat dissipation problems found in conventional LED devices. Some embodiments include a plurality of optically permissive layers, including an optically permissive cover substrate or wafer stacked over a semiconductor LED and positioned using one or more alignment markers.

Abstract: Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.

Abstract: There is provided a method for manufacturing a semiconductor device, including: providing a semiconductor substrate having a plurality of openings formed thereon by removing a sacrificial gate; filling the openings with a top metal layer having compressive stress; and performing amorphous doping with respect to the top metal layer in a PMOS device region. Thus, it is possible to effectively improve carrier mobility of an NMOS device, and also to reduce the compressive stress in the PMOS device region to ensure a desired performance of the PMOS device.

Abstract: A semiconductor device manufacturing method of the present invention includes a coating step of coating a front surface of a wafer with a material containing a solvent, a volatilization step of volatilizing the solvent by heating the material, and a rinse step of jetting an edge rinse solution for removing the material from a first nozzle to a peripheral portion of the front surface of the wafer while rotating the wafer.

Abstract: A structure of a conductive pad is provided. The structure includes a first conductive layer. A first dielectric layer covers the first conductive layer. A first contact hole is disposed within the first dielectric layer. A second conductive layer fills in the first conductive hole and extends from the first conductive hole to a top surface of the first dielectric layer so that the second conductive layer forms a step profile. A second dielectric layer covers the first dielectric layer and the second conductive layer. A third conductive layer contacts and covers the step profile.

Abstract: A semiconductor structure is provided that includes a silicon germanium alloy fin having a second germanium content located on a first portion of a substrate. The structure further includes a laterally graded silicon germanium alloy material portion located on a second portion of the substrate. The laterally graded silicon germanium alloy material portion is spaced apart from the silicon germanium alloy fin and has end portions having the second germanium content and a middle portion located between the end portions that has a first germanium content that is less than the second germanium content.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a stack structure on the interfacial layer; patterning the stack structure to form a gate structure on the interfacial layer; forming a liner on the interfacial layer and the gate structure; and removing part of the liner and part of the interfacial layer for forming a spacer.

Abstract: The present invention provides a method of forming an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

Abstract: A laser-induced thermal imaging apparatus includes a substrate support unit and a laser beam irradiation unit. The substrate support unit and the laser beam irradiation unit move relative to each other so that the substrate arranged on the substrate support unit is scanned in one direction by a laser beam irradiated from the laser beam irradiation unit. The laser beam irradiation unit includes a beam generation unit, a first mask arranged on a path of the linear laser beam generated in the beam generation unit, the first mask including a plurality of openings arranged along a length direction of the linear laser beam, and a shield unit movable to expose all of the plurality of openings of the first mask or to shield at least some of the plurality of the openings of the first mask.

Abstract: A manufacturing method of an organic light emitting device may include the following. A panel displaying an image is formed. A buffering member including a dummy buffering member is adhered to the panel. A film is adhered to an upper surface of the buffering member. The film and the dummy buffering member are removed.

Abstract: Methods for removing particles from a wafer for photolithography. A method is provided including providing a semiconductor wafer; attaching a polyimide layer to a backside of the semiconductor wafer; and performing an etch on an active surface of the semiconductor wafer; wherein particles that impinge on the backside during the etch are captured by the polyimide layer. In another method, includes attaching a layer of polyimide film to a backside of a semiconductor wafer; dry etching a material on an active surface of the semiconductor wafer; depositing of an additional layer of material on the active surface of the semiconductor wafer; removing the layer of polyimide film from the backside of the semiconductor wafer; patterning the layer of material using an immersion photolithography process to expose a photoresist on the active surface of the wafer; and repeating the attaching, dry etching, depositing, removing and patterning steps.

Abstract: Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a clamping electrode for electrostatically clamping the work piece to the work piece support; providing a mechanical partition between the plasma source and the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.

Abstract: A transistor may include a source region and a drain region separately formed in a substrate, a trench defined in the substrate between the source region and the drain region, and a buried gate electrode formed. The buried gate electrode includes a high work function liner layer having a bottom portion which is positioned over a bottom of the trench and sidewall portions which are positioned on lower sidewalls of the trench; a low work function liner layer positioned on upper sidewalls of the trench, and overlapping with the source region and the drain region; and a low resistance layer contacting the high work function liner layer and the low work function liner layer, and partially filling the trench.

Abstract: After forming a material stack including, from bottom to top, a dielectric material layer, a transfer layer, a hard mask layer and a neutral layer over a substrate, the neutral layer and the hard mask layer is patterned to create trenches therein that correspond to areas where unnecessary lines generated by a self-assembly of a self-assembling material subsequently formed and/or unnecessary portions of such lines are present. The self-assembling material is applied over the top surfaces of the patterned neutral layer and the transfer layer to form a self-aligned lamellar structure including alternating first and second domains. The second domains are removed selective to the first domains to provide a directed self-assembly (DSA) pattern of the first domains. Portions of the first domains not intersecting the trenches can be transferred into the patterned hard mask layer, resulting in a composite pattern of a pattern of trenches and the DSA pattern.

Abstract: A gate insulating film is provided on a trench. The gate insulating film has a trench insulating film and a bottom insulating film. The trench insulating film covers each of a side wall and a bottom portion. The bottom insulating film is provided on the bottom portion with a trench insulating film being interposed therebetween. The bottom insulating film has a carbon atom concentration lower than that of the trench insulating film. The gate electrode is in contact with a portion of the trench insulating film on the side wall. Accordingly, a low threshold voltage and a large breakdown voltage can be attained.

Abstract: Methods of forming a memory device having an array portion including a plurality of array transistors and a periphery region including peripheral circuit transistor structures of the memory device, where an upper surface of the periphery region and an upper surface of the array portion are planar (or nearly planar) after formation of the peripheral circuit transistor structures and a plurality of memory cells (formed over the array transistors). The method includes forming the peripheral circuit transistor structures in the periphery region, forming the plurality of array transistors in the array portion and forming a plurality of memory cells over respective vertical transistors. Structures formed by the method have planar upper surfaces of the periphery and array regions.

Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-? metal gate) integrated circuit which includes a high voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.

Abstract: The present disclosure relates to a method of forming a masking structure having a trench with a high aspect ratio, and an associated structure. In some embodiments, the method is performed by forming a first material over a substrate. The first material is selectively etched and a second material is formed onto the substrate at a position abutting sidewalls of the first material, resulting in a pillar of sacrificial material surrounded by a masking material. The pillar of sacrificial material is removed, resulting in a masking layer having a trench that extends into the masking material. Using the pillar of sacrificial material during formation of the trench allows the trench to have a high aspect ratio. For example, the sacrificial material allows for a plurality of masking layers to be iteratively formed to have laterally aligned openings that collectively form a trench extending through the masking layers.

Abstract: Integrated circuits and methods for producing the same are provided. In accordance with one embodiment a method of producing an integrated circuit includes forming a trench defined by a first material. The trench is filled with a second material to produce a gap defined within the second material, where the second material is in a solid state. The second material is reflowed within the trench to reduce a volume of the gap, and the second material is then solidified within the trench.