Abstract: An array substrate, a manufacturing method thereof and a display panel. After a metal layer is formed on a substrate, a protective layer is formed on the metal layer.

Abstract: An organic light-emitting diode (OLED) display panel includes a flexible substrate layer including a first area and two second area. A bending stress applied to the first area is greater than a bending stress applied to the second areas. A driver circuit layer is disposed on the second areas and non-bent areas. An organic planarization portion includes a first organic planarization layer disposed on the first area, and a second organic planarization layer disposed on the driver circuit layer and the first organic planarization layer. A light-emitting layer is disposed on the second organic planarization layer and located on the bent area and the non-bent areas.

Abstract: Dielets on flexible and stretchable packaging for microelectronics are provided. Configurations of flexible, stretchable, and twistable microelectronic packages are achieved by rendering chip layouts, including processors and memories, in distributed collections of dielets implemented on flexible and/or stretchable media. High-density communication between the dielets is achieved with various direct-bonding or hybrid bonding techniques that achieve high conductor count and very fine pitch on flexible substrates. An example process uses high-density interconnects direct-bonded or hybrid bonded between standard interfaces of dielets to create a flexible microelectronics package. In another example, a process uses high-density interconnections direct-bonded between native interconnects of the dielets to create the flexible microelectronics packages, without the standard interfaces.

Abstract: A method for manufacturing a switch-mode converter includes forming a plurality of windings by coiling one or more conductors. Each of the windings is secured to one of a plurality of module bases arranged in a module array. At least one side of the array is encapsulated in a magnetic mold compound.

Abstract: A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.

Abstract: A continuous inline method for production of photovoltaic devices at high speed includes: providing a substrate; depositing a first carrier transport solution layer with a first carrier transport deposition device to form a first carrier transport layer on the substrate; depositing a Perovskite solution comprising solvent and perovskite precursor materials with a Perovskite solution deposition device on the first carrier transport layer; drying the deposited Perovskite solution to form a Perovskite absorber layer; and depositing a second carrier transport solution with a second carrier transport deposition device to form a second carrier transport layer on the Perovskite absorber layer, wherein the deposited Perovskite solution is dried at least partially with a fast drying device which causes a conversion reaction and the Perovskite solution to change in optical density by at least a factor of 2 in less than 0.5 seconds after the fast drying device first acts on the Perovskite solution.

Abstract: A photodetection device includes a pixel matrix in which each pixel includes a barrier photodetector. The pixel matrix includes an absorption layer, a barrier layer, a contact layer, and at least one separation element to delimit the pixels. At least one separation element extends above the contact layer, and forms at least one depletion zone that extends locally in the contact layer, to block the lateral circulation of charge carriers.

Abstract: A multi-piece substrate integrally having a plurality of product regions each provided with a light-emitting element driven by a current and a blank region adjacent to each of the plurality of product regions is prepared. The current is passed through a cathode pad and an anode pad to inspect the light-emitting element. A plurality of display panels are cut out from the multi-piece substrate so as to respectively correspond to the plurality of product regions. The multi-piece substrate includes a plurality of first test pads disposed in each of the plurality of product regions for inspecting the light-emitting element, and a plurality of second test pads disposed in the blank region for inspecting the light-emitting element. The cathode pad and the anode pad are included in the plurality of first test pads and are not included in the plurality of second test pads.

Abstract: A sensor device includes a piezoresistive element that is formed in a semiconductor substrate and has a polarity opposite to a polarity of the semiconductor substrate, diffusion wirings that are formed in the semiconductor substrate and have a polarity opposite to the polarity of the semiconductor substrate, a first barrier layer formed between the adjacent diffusion wirings in the semiconductor substrate and has a same polarity as the polarity of the semiconductor substrate, and a second barrier layer that is formed on surface layers of the piezoresistive element and the diffusion wirings and have a same polarity as the polarity of the first barrier layer.

Abstract: A light emitting device includes: a base comprising a first lead, a second lead, and a supporting member; a light emitting element mounted on the first lead; a protection element mounted on the second lead; a wire including a first end and a second end, wherein the first end is connected to an upper surface of the first lead, and the second end is connected to a first terminal electrode of the protection element; a resin frame located on an upper surface of the base, wherein the resin frame covers at least part of the protection element and surrounds the light emitting element and the first end of the wire; a first resin member surrounded by the resin frame and covering the light emitting element and the first end of the wire; and a second resin member covering the resin frame and the first resin member.

Abstract: The present disclosure relates to a perovskite that includes ABX3, where A is an organic cation, B is a second cation, X is an anion, and the perovskite has a film density (?) of less than 4.37 g/cm3. In some embodiments of the present disclosure, the film density may be in the range, 4.1 g/cm3???4.37 g/cm3. In some embodiments of the present disclosure, the organic cation may include at least one of dimethylammonium (DMA), guanidinium (GA), and/or acetamidinium (Ac). In some embodiments of the present disclosure, A may further include cesium.

Abstract: A mother substrate and a display panel are disclosed. The mother substrate includes a plurality of display panels, a plurality of first test terminals and a plurality of first one-way conductive circuits. Each of the display panels has a display area, and includes a plurality of first signal lines extending from outside of the display area to the display area in parallel; the plurality of first signal lines of each of the display panels are respectively electrically connected to one of the plurality of first test terminals; the plurality of first one-way conductive circuits are respectively electrically connected to the plurality of first signal lines outside the display area and are configured to allow signals to be able to transmit only from the plurality of first test terminals to the plurality of first signal lines of each of the display panels.

Abstract: A method is presented for employing contact over active gate to reduce parasitic capacitance. The method includes forming high-k metal gates (HKMGs) between stacked spacers, the stacked spacers including a low-k dielectric lower portion and a sacrificial upper portion, forming a first dielectric over the HKMGs, forming first contacts to source/drain of a transistor between the HKMGs, and forming a second dielectric over the first contacts. The method further includes selectively removing the first dielectric to form second contacts to the HKMGs, selectively removing the second dielectric to form third contacts on top of the first contacts, removing the sacrificial upper portion of the stacked spacers, and depositing a third dielectric that pinches off the remaining first and second dielectrics to form air-gaps between the first contacts and the HKMGs.

Abstract: A method for fabricating an active cooling structure, comprising forming an array of Superconductor-Insulator-Normal Metal (NIS) tunnel structures between a non-conducting layer and a superconducting layer. The non-superconducting layer may comprise a plurality of non-superconducting traces running in a first direction. The superconductor layer may comprise a plurality of superconducting traces running in a second direction.

Abstract: The present invention provides an organic light-emitting element, comprising a substrate, a first electrode, more than one organic layer film comprising a light-emitting layer, and a second electrode. The light-emitting element further comprises a cover layer. The cover layer is located on the second electrode, and comprises a high refractive layer and a low refractive layer. A material for the low refractive layer of the cover layer is a boron complex organic small molecular compound. The organic light-emitting element provided by the present invention can achieve high light-emitting efficiency and color reproducibility. The organic light-emitting element of the present invention can be used for an organic EL display, a backlight source of a liquid crystal display, illumination, a sign board, an identification lamp, etc.

Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.

Abstract: A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.

Abstract: An electronic apparatus is provided. The electronic apparatus includes a substrate including a plurality of electrodes in contact with at least part of electrodes of a plurality of micro LEDs disposed on a transparent substrate at a first pitch to apply a current to micro LEDs of the plurality of micro LEDs disposed at a second pitch, a camera disposed opposite to the substrate based on the transparent substrate, and a processor configured to apply a current to the plurality of electrodes on the substrate, control the camera to capture an image of the plurality of LEDs including a light emitting micro LED according to current applying, obtain characteristic information of the light emitting micro LED based on the captured image, and determine a target substrate on which each of the plurality of micro LEDs is disposed based on the obtained characteristic information.

Abstract: An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more inter connect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.

Abstract: An organic substrate and method of making with optimal thermal warp characteristics is disclosed. The organic substrate has one or more top layers and one or more bottom layers. A chip footprint region is a surface region on each of the top and bottom layers that is defined as the projection of one or more semiconductor chips (chips) on the surface of each of the top and bottom layers. One or more top removal patterns are located on and may or may not remove material from the surface of one or more of the top layers within the chip footprint region of the respective top layer. One or more bottom removal patterns are located on and remove material from the surface of one or more of the bottom layers outside the chip footprint region of the respective bottom layer. The removal of the material from one or more of the top layers and/or bottom layers changes and optimizes a thermal warp of the organic substrate.