Patents Examined by Ernest Karlsen
  • Patent number: 7164262
    Abstract: A typical probe comprises a sensor, and a connection head that includes a conversion circuit for driving the sensor. The probe communicates with a controller via a two wire DC 4-20 mA link. The conversion circuit is also known as a two-wire transmitter. The conversion circuit and the sensor are connected to each other (and to the external link) via screw terminals usually located at the circuit top face. The invention provides a conversion circuit and a matching base forming plug and socket type connections. On the converter circuit, the connections are moved from the top of the circuit, to the bottom of the circuit, thus clearing space for an integral display. The sensor and the link wires are attached to the base socket. The conversion circuit fits into the socket in only a single orientation, thus ensuring correct coupling of the wires to the circuit elements.
    Type: Grant
    Filed: March 10, 2004
    Date of Patent: January 16, 2007
    Inventor: Ely Zacay
  • Patent number: 7161369
    Abstract: A method and apparatus for a wiping fixture probe for cleaning oxides, residues or other contaminants from the surface of a solder bead probe and probing a solder bead probe on a printed circuit board during in-circuit testing.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: January 9, 2007
    Assignee: Agilent Technologies, Inc.
    Inventors: Kenneth P. Parker, Richard W. Rivas, Sr.
  • Patent number: 7161373
    Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: January 9, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Tim J. Corbett
  • Patent number: 7161365
    Abstract: An apparatus for enabling connection to a ground plane of a test board during the testing of contacts on the board, comprising a conductive ground plate overlying said ground plane having at least one opening which overlies contacts on the board to be tested, the ground plate having a top side and an underside, there being at least one conductive abutment on the underside of the ground plate which contacts the ground plane, whereby connection to the ground plane may be made by contacting the top side of the ground plate during testing of the contacts.
    Type: Grant
    Filed: November 4, 2004
    Date of Patent: January 9, 2007
    Assignee: Infineon Technologies AG
    Inventors: Josef Gluch, Boris Safin, David Karasiewicz
  • Patent number: 7157928
    Abstract: One embodiment of this invention pertains to a high throughput screening technique to identify current leakage in matrix-structured electronic devices. Because elements that are likely to develop a short have relatively high leakage current at zero operation hours, by identifying elements with the relatively high leakage current, the electronic devices that are more likely to later develop a short can be differentiated. The screening technique includes performing the following actions: selecting one of multiple first lines; applying a first voltage to the selected first line; applying a second voltage to the one or more of the first lines that are not selected; floating the multiple second lines; and measuring the voltages on the second lines, either sequentially one line at a time or measuring all the lines at the same time.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: January 2, 2007
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Franky So, Florian Pschenitzka, Egbert Hoefling
  • Patent number: 7148674
    Abstract: A leakage current measurement apparatus for measuring leakage currents is disclosed. The leakage current measurement apparatus automatically selects one of non-inductive shunt resistors of 10?, 100?, and 1000? and measures leakage currents of an outdoor isolation material for an ultra-high voltage. Additionally, the leakage current measurement apparatus is capable of measuring a relatively wide range of leakage currents with a relatively high precision, even at a remote location, as a measurement range is automatically adjusted within measurement ranges preset by a user when leakage currents of an outdoor isolation material change, and being protected against a surge possibly generated by an ultra-high voltage. Also, it can remotely measure in real-time leakage currents of an outdoor isolation material installed at a remote location over Ethernet.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: December 12, 2006
    Assignee: Korea Electric Power Corporation
    Inventors: In Hyuk Choi, Dong Il Lee, Jeong Shik Ahn, Gil Jo Jung, Jang Hyun Choi
  • Patent number: 7148705
    Abstract: The charging voltage measuring device includes a measuring electrode for forming an electrostatic capacity Cs with a substrate disposed on a substrate holding unit, a measuring capacitor, which has an electrostatic capacity Cm, being connected between the measuring electrode and a ground potential portion, and, a voltage measuring unit for measuring a measuring voltage Vm across the measuring capacitor, and a calculating unit. The calculating unit 22 calculates the charging voltage Vs on the surface of the substrate at time t1 in accordance with the following numerical expression on the basis of the measuring voltage Vm(t1) at time t1, an inverse K of a voltage dividing ratio and a resistance value Rm of a resistor disposed in parallel to the measuring capacitor 18, when the measurement time is t1 Vs=K[Vm(t1)+{1/(Cm·Rm)}?0t1Vm(t)dt] where K=(Cs+Cm)/Cs or K=Cm/Cs (if Cm>>Cs).
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: December 12, 2006
    Assignee: Nissin Ion Equipment Co., Ltd.
    Inventor: Shuichi Maeno
  • Patent number: 7145323
    Abstract: Apparatus and methods are provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network analyzer in conjunction with a coaxial test probe. Simple, low-cost test fixturing and methods of testing may be used to measure the parasitic capacitance and inductance of one or more I/O leads of an integrated circuit package, the measured parasitic capacitances and inductances providing an indication of the susceptibility of the integrated circuit package to mutual coupling between electrical leads of the package or between an electrical lead and other components of the integrated circuit package.
    Type: Grant
    Filed: August 23, 2004
    Date of Patent: December 5, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Mark T. Van Horn, Richard N. Hedden, David R. Cuthbert, Aaron M. Schoenfeld
  • Patent number: 7145353
    Abstract: A probe head for testing the properties of a semiconducting device (10) under test including a dielectric film (24) supporting at least one semiconducting device (10) under test with a support frame (26) tautly supporting the dielectric film (24). A first support (40) positions a first probe (28) for electrically contacting a first side (16) of the semiconducting device (10) under test and a second support (34), having a actuator to move a second probe (30) between a first position (P1) and a second position (P2), positions second probe (30) with the second position (P2) being for electrically contacting an opposing second side (18) of the semiconductor device under test.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: December 5, 2006
    Assignee: Wentworth Laboratories, Inc.
    Inventors: Jeremy Hope, Adrian R. Overall, John J. Fitzpatrick
  • Patent number: 7141997
    Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: November 28, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Tim J. Corbett
  • Patent number: 7141994
    Abstract: An electrical component testing device comprising a housing having at least one recess covered by a flexible membrane so as to form a chamber. A fluid passage extends through a portion of the housing and connects to the chamber thus permitting passage of a fluid material into the chamber. At least one contact member is positioned on the flexible membrane so as to provide an electrical connection to an electrical contact on a device to be tested.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: November 28, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Salman Akram
  • Patent number: 7142000
    Abstract: Resilient contact structures are mounted directly to bond pads on semiconductor dies, prior to the dies being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies to be exercised (e.g., tested and/or burned-in) by connecting to the semiconductor dies with a circuit board or the like having a plurality of terminals disposed on a surface thereof. Subsequently, the semiconductor dies may be singulated from the semiconductor wafer, whereupon the same resilient contact structures can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements of the present invention as the resilient contact structures, burn-in can be performed at temperatures of at least 150° C., and can be completed in less than 60 minutes.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: November 28, 2006
    Assignee: FormFactor, Inc.
    Inventors: Benjamin N. Eldridge, Gary W. Grube, Igor Y. Khandros, Gaetan L. Mathieu
  • Patent number: 7138812
    Abstract: Provided is a probe card including: a printed circuit board comprising a ground electrode; at least one dielectric disposed below the ground electrode; and a plurality of needles, each of which comprises: a first end portion contacting a wafer pad of a semiconductor device, a second end portion electrically connected to the printed circuit board, and the remaining portion excepting the first and second end portions surrounded by the at least one dielectric. A metal plate is disposed below the at least one dielectric; and a connecting pin electrically connects the metal plate to the ground electrode and fixes the at least one dielectric and the metal plate to the printed circuit board.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: November 21, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Il-Chan Park, Young-bu Kim, Du-sik Yoo
  • Patent number: 7138811
    Abstract: A system for reducing condensation during testing of an integrated circuit is disclosed. An exemplary embodiment includes two seals which close both ends of an enclosed channel formed when the load board is secured to the device tester. Clean dry air with a pressure greater than that of the environment is feed into the enclosed channel and is trapped because of the seals.
    Type: Grant
    Filed: July 1, 2005
    Date of Patent: November 21, 2006
    Assignee: Xilinx, Inc.
    Inventors: David M. Mahoney, Mohsen Hossein Mardi
  • Patent number: 7135875
    Abstract: The invention relates to methods for positioning of a substrate 140 and contacting of the test object 301 for testing with a test apparatus with an optical axis and corresponding devices. Thereby, the substrate is put on the holder 130. The substrate is positioned relative to the optical axis. A contact unit 150 is also positioned relative to the optical axis, whereby the contact unit is positioned independent of the positioning activity of the substrate. Thereby, a flexible contacting of test objects on the substrate can be realized.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: November 14, 2006
    Assignee: Applied Materials GmbH
    Inventor: Matthias Brunner
  • Patent number: 7135849
    Abstract: An extremal voltage detector produces an output voltage from an operational amplifier having its non-inverting input terminal connected to a first node and its inverting input terminal connected to a second node. A number of identical metal-oxide-semiconductor field-effect transistors (MOSFETs) controlled by respective input voltages are connected in parallel between the first node and a first power supply terminal. Another identical MOSFET, controlled by the output voltage, is connected between the second node and the first power supply terminal. Alternatively, a plurality of identical MOSFET detection circuits, controlled by the input and output voltages, are connected in parallel between the first power supply node and the first and second nodes. A pair of constant-current circuits conduct equal currents from the first and second nodes to a second power-supply terminal.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: November 14, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Syouhei Yamamoto
  • Patent number: 7135880
    Abstract: A waveform formatter according to the present invention includes a first delay circuit for delaying a set signal to control the timing of a first change point of a test signal, a second delay circuit for delaying a reset signal to control the timing of a second change point of the test signal changed by the set signal which the first delay circuit delays, a third delay circuit for delaying a set signal to control the timing of a third change point of the test signal, a fourth delay circuit for delaying a reset signal to control the timing of a fourth change point of the test signal changed by the set signal which is delayed by the third delay circuit, a fifth delay circuit for delaying a set signal to control the timing of a first change point of an enable signal of the driver, a sixth delay circuit for delaying a reset signal to control the timing of a second change point of an enable signal with regard to the driver during a predetermined cycle of a cycle reference signal.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: November 14, 2006
    Assignee: Advantest Corporation
    Inventor: Toshiyuki Negishi
  • Patent number: 7132842
    Abstract: For an inspection of a display device which incorporates a driver circuit around pixels, a start pulse and a clock pulse are required to be inputted as inspection signals. The more complex the driver circuit is, the more complexity the start pulse and the clock pulse tend to have, which will increase the manufacturing cost of inspection signals. In addition, since a clock generator is required, cost of an inspection device is increased. Furthermore, it will lead to a longer inspection time. By setting all the power supplies for the driver circuit at a desired potential, a desired potential is outputted regardless of an input signal.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: November 7, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Keisuke Miyagawa
  • Patent number: 7129728
    Abstract: There is provided an LSI socket containing a pogo-pin type decoupling capacitor for reducing the potential fluctuation of power supplies and GNDs at the time of testing LSI incorporated in a BGA package. The LSI socket comprises a printed board 102 containing decoupling capacitors 113 corresponding to one or more power supply voltages inside thereof, a pogo-pin supporting casing portion 104 on which the printed board 102 is overlapped into a single piece, and pogo-pins 103 inserted into penetrating holes in which hole positions of through holes 109 drilled in the printed board 102 and casing holes 114 drilled in the pogo-pin supporting casing portion 104 are allowed to be matched, wherein the printed board 102 is disposed on the upper surface side of the pogo-pin supporting casing portion 104 which faces the BGA package, or disposed on the lower surface side of the pogo-pin supporting casing portion 104, at the time of testing the LSI incorporated in the BGA package.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: October 31, 2006
    Assignee: NEC Corporation
    Inventor: Yasushi Kinoshita
  • Patent number: 7129691
    Abstract: A low-cost, current sensor suitable for mass production and a manufacturing method thereof are provided. The current sensor is small with high sensitivity and can be packaged in a standard assembly line which is normally used when an integrated circuit is manufactured. Further, it is possible to obtain a sufficient shielding effect against a disturbance flux without degrading the detecting sensitivity of a flux. A first magnetic material 50 is bonded to the lower part of a current conductor 22C. The first magnetic material 50 has the function of converging and amplifying a flux 3 generated by the current to be measured. A second magnetic material 51 is bonded above a magnetic sensor chip 20. The second magnetic material 51 has a shielding function against a disturbance flux entering from the outside.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: October 31, 2006
    Assignees: Sentron AG, Asahi Kasei EMD Corporation
    Inventors: Koji Shibahara, Radivoje Popovic, Yo Yamagata, Robert Racz