Abstract: An interconnection contact structure assembly including an electronic component having a surface and a conductive contact carried by the electronic component and accessible at the surface. The contact structure includes an internal flexible elongate member having first and second ends and with the first end forming a first intimate bond to the surface of said conductive contact terminal without the use of a separate bonding material. An electrically conductive shell is provided and is formed of at least one layer of a conductive material enveloping the elongate member and forming a second intimate bond with at least a portion of the conductive contact terminal immediately adjacent the first intimate bond.

Abstract: In the electroconductive contact unit of the present invention, a gold plated layer 8 is formed over the surface of an electroconductive needle member 2 via a Ni under layer 7a, and a layer of iridium (titanium nitride, rhodium or hafnium nitride) is formed on the gold plated layer 8 of the needle portion 2a by sputtering, via an Ni under layer 7b. Thereby, the tip portion is provided with an improved resistance to oxidization and wear without using any special material for the needle member, and the durability of the needle member is improved so that the running cost can be minimized.

Abstract: Testing of a system-on-a-chip having a programmable section and a plurality of high-speed interfaces begins by configuring the programmable section to support a 1st level testing of the plurality of high-speed interfaces. The testing continues by testing one of the plurality of high-speed interfaces at the 1st level of testing via the programmable section. The testing continues by evaluating the tested performance characteristics in accordance with the prescribed performance characteristics of the standard to determine whether the one of the plurality of high-speed interfaces conforms with the standard requirements. When the one of the plurality of high-speed interfaces conforms with the standard requirements, the plurality of high-speed interfaces are configured for a 2nd level testing, where the 1st level testing is more stringent than the 2nd level testing. The testing continues by testing, at the 2nd level, remaining ones of the plurality of high-speed interfaces.

Abstract: An electric current measurement device includes a housing defining first and second open ends sealed by first and second sealing means, respectively; a first optical fibre received in an aperture in the first sealing means and in optical communication with a first optical lens in the housing; a first polarisation filter in the housing in optical communication with the first lens; a magneto-optical rod within the housing in optical communication with the first polarisation filter; a second polarisation filter in the housing in optical communication with the rod; and a second optical lens in the housing in optical communication with the second polarisation filter. The second sealing means has an aperture for receiving a second optical fibre fixed to the second lens. First and second lids, attachable to the first and second housing ends, respectively, include apertures for receiving the first and second optical fibres, respectively.

Abstract: An integrated circuit for use at a reduced Vdd voltage. An integrated circuit is designed and implemented such that it is usable at a voltage less than an industry standard Vdd voltage. The integrated circuit may include a voltage filter that may either be implemented on the integrated circuit or external to the integrated circuit. The voltage filter receives an industry standard IC voltage and produces a filtered voltage that is that some value below the industry standard IC voltage. The voltage filter also removes noise from the industry standard IC voltage. The integrated circuit includes signal processing circuitry that is designed and implemented to improve signal quality and to operate at the filtered voltage.

Abstract: An interposer probe includes a main board having a first side and a second side. A lower riser board mounted to the first side of the main board and in electrical contact therewith is configured to engage an integrated circuit socket on a device to be tested. An upper riser board mounted to the second side of said main board and in electrical contact therewith, is configured to receive an integrated circuit package. A retention frame mounted to the first side of said main board engages the integrated circuit socket on the device to be tested.

Abstract: A method and apparatus allows adapting a standard flying prober system to probe test point targets on Printed Circuit Assemblies (PCAs) having irregularities in their planarity. The method and apparatus involves positioning a camera utilized by the prober system to predetermined offset positions relative to previously established test and/or other points for sets of images. Each set of images is processed by determining offsets in coordinates needed to align the images in a predetermined manner. The offsets for each measured point are translated into actual height values to be used during subsequent testing of a PCA.

Abstract: A system and method for sensing the proximity of an electronic device, in particular, a radio frequency mobile communication device such as a mobile telephone, wireless modem equipped portable computer, or the like to a body employs an antenna capable of altering its impedance for changing the amount of radio frequency electromagnetic energy reflected by the antenna when the antenna is in proximity to the body. The radio frequency electromagnetic energy reflected by the antenna is measured and used for determining proximity of the antenna to the body.

Abstract: High port-to-port RF isolation for a test socket in a production RF test environment is achieved by establishing a coaxial-type connection between the test socket and the device under test (DUT). This coaxial-type connection results by at least partially surrounding each port of the DUT with a ground seal connected to RF ground connection. In one embodiment, the ground seal is a metallic base plate of the test socket which surrounds the RF connection to the DUT.

Abstract: An integrated circuit functionality test determining shorts between adjacent pins of all the IC pins while simultaneously determining pin continuity in only three steps. The process includes categorizing all pins of the IC into three sets of pins. One set of pins is connected to digital instruments, a second set of pins is connected to 0 volts, and a third set of pins is left open. The digital instruments sink current in parallel from the first set of pins to identify any shorts of the first set of pins. The process is repeated for each of the other two sets of pins. For IC packages having double and quad terminal positions, each terminal position is treated like a single terminal position, and the measurements of the respective sets of pins of each terminal position is measured in parallel.

Abstract: In one embodiment, the invention provides a test assembly for electrically connecting a test component to a testing machine for testing electrical circuits on the test component. The assembly comprises a contactor assembly to interconnect with the test component, a probe assembly to mechanically support the contactor assembly and electrically connect the contactor assembly to the testing machine, and a clamping mechanism comprising a first clamping member and a second clamping member, the clamping members being urged together to exert a clamping force to deform contactor bumps of an electrical connection between the probe assembly and the contactor assembly.

Abstract: The invention, which relates to a test apparatus with loading device which has a chuck, which is provided with a bearing surface for a test substrate and with a chuck drive, by means of which the chuck can be displaced with a working area, and which has a receiving means for receiving test substrates, which can be displaced from a working area of the chuck to a receiving position outside the working area, is based on the object of increasing the accuracy of the movement of the chuck. Moreover, in the case of test apparatus with a controlled atmosphere, a further object is to prevent the chuck from being exposed to the open-air atmosphere.

Abstract: A contact system for electrically engaging semiconductor components includes an interface board mountable to an automated test handler, and a floating substrate on the interface board. The interface board includes interface contacts in electrical communication with external test circuitry. The substrate includes flexible segments, and contactors having contact pads on opposing sides of the flexible segments configured to simultaneously electrically engage terminal contacts on the components, and the interface contacts on the interface board. The contact pads include conductive polymer layers that provide an increased compliancy for the contactors. This increased compliancy allows the contactors to accommodate variations in the dimensions and planarity of the terminal contacts on the component. In addition, the substrate includes grooves between the contactors which provide electrical isolation and allow the contactors to move independently of one another.

Abstract: A power solid-state device is pulsed from a controlled pulse source, which generates heat in the chip. Similar or identical pulses are applied to a software or equivalent electrical hardware temperature simulator, for predicting the chip temperature. The output of the simulator is monitored, and the controlled pulse source is inhibited in the event that the predicted chip temperature exceeds a limit. A delay may be introduced between the pulse generation and application to the chip. Additional temperatures associated with the chip heat sink may be combined with the chip temperature.

Abstract: The invention relates to an integrated test circuit in an integrated circuit for testing a plurality of internal voltages. A switching device is provided to select one of the internal voltages in accordance with a selection signal for the purpose of testing, and a comparator device is provided in order to compare a measurement voltage, dependent on the selected internal voltage, with an externally provided reference voltage. An error signal is output as a result of the comparison.

Abstract: To make possible the in-line inspection of a pattern of an insulating material. A patterned wafer 40 formed with a pattern by a resist film is placed on a specimen table 21 of a patterned wafer inspection apparatus 1 in opposed relation to a SEM 3. An electron beam 10 of a large current is emitted from an electron gun 11 and the pattern of the patterned wafer is scanned only once at a high scanning rate. The secondary electrons generated by this scanning from the patterned wafer are detected by a secondary electron detector 16 thereby to acquire an electron beam image. Using this electron beam image, the comparative inspection is conducted on the patterned wafer through an arithmetic operation unit 32 and a defect determining unit 33. Since an electron beam image of high contrast can be obtained by scanning an electron beam only once, a patterned wafer inspection method using a SEM can be implemented in the IC fabrication method.

Abstract: A method is provided of setting grids and/or markers on a screen of a display unit of a measuring apparatus. First, a mode of the apparatus is changed into a mode of setting the grids and/or the markers. Then, the grid and/or the marker serving as a reference is set. Then, a plurality of grids and/or markers are set, each of which provides an arbitrary interval with respect to the grid and/or the marker serving as reference.

Abstract: Disclosed is a method of inspecting a sample. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.

Abstract: Wafer-level testing is performed on an electronic device to be used in an optical communications system. An optical test signal is generated and is provided to a first photo detector. An electrical output of the first photo detector is supplied to the electronic device on the wafer. An electrical output from the electronic device on the wafer is used to drive a light source. An optical output of the light source is supplied to a second photo detector and an electrical signal output from the second photo detector is examined.

Abstract: A method and apparatus tests a flat display device to inspect for shorts and open circuits in a signal wire by using a magnetic sensor. The inspection method and apparatus scans the magnetic sensor along signal wires in a scan direction crossing multiple signal wires and detects at least one of a short or an open circuit in the signal wires based on current detected by the magnetic sensor.