Patents Examined by Ernest Karlsen
  • Patent number: 7129723
    Abstract: A test device for electrical testing of a unit under test, the device having a contact head which can be associated with the unit under test and is provided with contact elements pins in a contact pin arrangement, having an electrical connecting apparatus, including contact surfaces which make touching contact with first ends of the contact elements which face away from the test plane accommodating the unit under test, and having a supporting apparatus which is arranged on the side of the connecting apparatus facing away from the contact head. Pulling or pushing devices adjust the planar condition or a desired discrepancy from the planar condition of an arrangement of the contact surfaces and those devices are arranged between the supporting apparatus and the connecting apparatus.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: October 31, 2006
    Assignee: Feinmetall GmbH
    Inventor: Gunther Bohm
  • Patent number: 7129730
    Abstract: A modularized probe head assembly mainly includes a probe head, an interposer and a probe head carrier with guide pins. The probe head has a plurality of first through holes. The interposer has a plurality of second through holes corresponding in location to the first through holes. The probe head carrier is configured to secure the PCB of a probe card and jointing the probe head with the interposer. A via is formed under a pad on the interposer. A plurality of stud bumps are formed on the pad. After assembling of the probe card, the guide pins pass through the first and second through holes and the stud bumps electrically contact the interconnect pad of the probe head.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: October 31, 2006
    Assignees: ChipMOS Technologies (Bermuda) Ltd., ChipMOS Technologies Inc.
    Inventors: An-Hong Liu, Yeong-Her Wang, Yeong-Ching Chao, Yao-Jung Lee
  • Patent number: 7123036
    Abstract: A pass through test system for testing an electronic module includes an interface board, and test contactors movably mounted to the interface board for electrically engaging terminal contacts on the module with a zero insertion force on the modules. The interface board is configured for mounting to an automated or manual pass through test handler in electrical communication with test circuitry. In a first embodiment the interface board includes test pads in electrical communication with the test circuitry, and rotatable test contactors having spring contacts configured to simultaneously engage the test pads and the terminal contacts on the module. In a second embodiment the interface board includes test pads in electrical communication with the test circuitry, and slidable test contactors having beam leads configured to simultaneously engage the test pads and the terminal contacts on the module.
    Type: Grant
    Filed: October 11, 2004
    Date of Patent: October 17, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Daniel P. Cram
  • Patent number: 7112976
    Abstract: Two resilient sections are connected to a tip end which is to be brought into contact with an external connection terminal of a contact belonging to a test socket of an electronic device or semiconductor package. The resilient sections provided opposite to each other and are bent so as to extend horizontally with respect to the tip end. The force exerted downward on the tip end is equally distributed between the plurality of resilient sections. The resilient sections are eventually deflected downwardly without involvement of horizontal sliding action. The force which is exerted on the tip end in reaction to the downward deflection of the curved portions brings the tip end into pressing contact with the external connection terminal without involvement of horizontal sliding action of the tip end with respect to the external connection terminal.
    Type: Grant
    Filed: May 11, 2004
    Date of Patent: September 26, 2006
    Assignee: Misubishi Denki Kabushiki Kaisha
    Inventors: Yasushi Tokumo, Shigeki Maekawa, Yoshihiro Kashiba, Shigeru Takada
  • Patent number: 7112986
    Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: September 26, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Tim J. Corbett
  • Patent number: 7112985
    Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: September 26, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Tim J. Corbett
  • Patent number: 7109738
    Abstract: A method for testing a partially fabricated wafer is provided that comprises the following steps: providing a device under test (DUT) and three reference oscillators overlying a substrate of the wafer; measuring the frequencies of the reference oscillators as influenced by transistor characteristics, intra structure parasitics, resistive, capacitive and inductive parasitics; and isolating the inductive parasitics by the appropriate comparisons between the reference oscillators.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: September 19, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Nagaraj Narasimh Savithri
  • Patent number: 7109734
    Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: September 19, 2006
    Assignee: Xilinx, Inc.
    Inventors: Xiao-Jie Yuan, Michael J. Hart, Zicheng G. Ling, Steven P. Young
  • Patent number: 7106084
    Abstract: A method of screening a semiconductor device comprises the steps of successively forming a gate insulation film (102) and a conductive film (104) on a silicon wafer (100) to provide a structure (106) and bringing the first voltage application terminal (110) into contact with the back of the structure and the second voltage application terminal (112) having a potential different from that of the first voltage application terminal (110) into contact with the surface of the conductive film (104) to thereby apply a stress voltage to the structure (106).
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: September 12, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Kiyohisa Fukaya
  • Patent number: 7102374
    Abstract: A micro-spray cooling system beneficial for use in testers of electrically stimulated integrated circuit chips is disclosed. The system includes micro-spray heads disposed about a probe head. The spray heads and probe head are disposed in a sealed manner inside a spray chamber that, during operation, is urged in a sealing manner onto a sealing plate holding the integrated circuit under test. The atomized mist cools the integrated circuit and then condenses on the spray chamber wall. The condensed fluid is pumped out of the chamber and is circulated in a chiller, so as to be re-circulated and injected again into the micro-spray heads. The pressure inside the spray chamber may be controlled to provide a desired boiling point.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: September 5, 2006
    Inventors: Tahir Cader, Charles Lester Tilton, Benjamin Hewett Tolman, George Joseph Wos, Alan Brent Roberts, Thomas Wong, Jonathan D. Frank
  • Patent number: 7102344
    Abstract: A circuit testing device includes a housing that is sized and adapted to securely fit into a light bulb socket. The device includes spring-loaded prongs which securely hold the housing in place in the socket until it is desired to remove the testing device. The testing device generates an audible signal when power is applied to the socket to alert a user that power is present, even if the user is located at a distance from the point of test.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: September 5, 2006
    Inventor: Barry W. F. Short
  • Patent number: 7098647
    Abstract: A testing apparatus for testing a device under test, includes a power source for generating a current, a coaxial cable unit for supplying the current to the device under test, a detecting unit for detecting a voltage applied to the device under test when the current is supplied to the device under test and a judging unit for judging quality of the device under test based on the detected voltage, wherein the coaxial cable unit includes a first coaxial cable including a first internal conductor and a first external conductor, and a second coaxial cable including a second internal conductor and a second external conductor, wherein the first internal conductor and the second external conductor conduct a current from the power source towards the device under test, and the first external conductor and the second internal conductor conduct a current from the device under test towards the power source.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: August 29, 2006
    Assignee: Advantest Corporation
    Inventors: Hironori Tanaka, Kunihiro Matsuura, Satoshi Kodera, Hiroki Ando, Yasuhiro Urabe
  • Patent number: 7098649
    Abstract: The invention provides a method of testing a circuit on a substrate. Generally speaking, a substrate is located in a transfer chuck, a surface of a test chuck is moved into contact with a substrate, the substrate is secured to the test chuck, the test chuck is moved relative to the transfer chuck so that the substrate moves off the transfer chuck, terminals on the substrate are moved into contact with contacts to electrically connect the circuit through the terminals and the contacts to an electric tester, signals are relayed through the terminal and the contacts between the electric tester and the circuit, the terminals are disengaged from the contacts, and the substrate is removed from the test chuck.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: August 29, 2006
    Assignee: Electroglas, Inc.
    Inventors: Timothy J. Boyle, Wayne E. Richter, Ladd T. Johnson, Lawrence A. Tom
  • Patent number: 7091735
    Abstract: A testing probe includes a first sleeve, a first springy component, a first movable rod, a second springy component, and at least one second movable rod. The first sleeve has a first containing portion, which is located inside the first containing portion. The first movable rod is partially inserted into the first containing portion, and has a first stopper portion and a second containing portion. The first stopper portion is located inside the first containing portion and contacts the first springy component, so that the first movable rod and first containing portion are capable of relatively sliding. The second springy component is located inside the second containing portion. The second movable rod is partially inserted into the second containing portion, and has a second stopper portion. The second stopper portion is located inside the second containing portion and contacts the second springy component, so that the second movable rod and second containing portion are capable of relatively sliding.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: August 15, 2006
    Assignee: Asustek Computer Inc.
    Inventors: Chung-Shan Lee, Hsu-Lin Ting
  • Patent number: 7091734
    Abstract: In the electroconductive contact unit of the present invention, an electroconductive needle member 2 is made of a noble metal alloy having a high hardness and wear resistance, and formed with a gold plated layer 8 via a Ni under layer 7, and a flat surface 2e is formed by a tip portion thereof so as to expose the material of the needle member. Thereby, the durability of the needle member is ensured and the electroconductivity of the electric path between the needle member and coil spring is minimized on account of the gold plated layer. Even when the contact surface is soiled by solder deposition after repeated applications to contact objects such as solder balls, simply grinding the contact surface and revealing a new surface, the contact resistance between the contact surface and contact object can be kept unchanged by grinding so that the test can be conducted with the benefit of low resistance at all times.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: August 15, 2006
    Assignee: NHK Spring Co., Ltd.
    Inventor: Toshio Kazama
  • Patent number: 7088089
    Abstract: A power detector for measuring the average power, without constant voltage, of modulated or unmodulated high frequency or microwave signals is described. The power detector includes a signal line connected to a high frequency input. A detection line is capacitively and/or inductively coupled to the signal line and, seen in the longitudinal direction, is connected to the signal line. The signal is tapped from the detection line at two or more detection positions which are staggered in the longitudinal direction.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: August 8, 2006
    Assignee: Rohde & Schware GmbH & Co. KG
    Inventors: Gerd Hechtfischer, Michael Katzer
  • Patent number: 7088122
    Abstract: The invention relates to a test arrangement for testing semiconductor circuit chips, in which a test signal received via a primary test channel from a driver amplifier of an item of test equipment is distributed via parallel sub-channels to a plurality of inputs of one or more semiconductor circuit chips under test the test arrangement having signal buffering circuits arranged in each sub-channel that receive and buffer the test signal from the driver amplifier before feeding it to the inputs of the semiconductor circuit chip(s).
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: August 8, 2006
    Assignee: Infineon Technologies AG
    Inventors: Udo Hartmann, Thierry Canaud
  • Patent number: 7088119
    Abstract: A mechanism for testing a printed circuit board. The mechanism includes a holder, an expansion board and at least one fixing member. The expansion board has a first edge where a contact zone is provided. The expansion board is partially disposed in the holder with the first edge thereof exposed. The first edge of the expansion board is inserted into an expansion slot of the printed circuit board, while the contact zone provides electrical connection to the expansion slot. The fixing member fixes the expansion board in the holder.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: August 8, 2006
    Assignee: ASUSTek Computer Inc.
    Inventor: Hsiao-Chen Lee
  • Patent number: 7084657
    Abstract: A probe card used for establishing electric contact with an electric part to inspect an electric characteristic thereof comprises a plurality of conductors, each transmitting a signal used for inspection, and a plurality of bumps, each formed on one of the plurality of conductors, which are used for establishing mechanical contact with the electric part. Each bump includes a lower portion fusedly arranged on the conductor and an upper portion taperedly formed in such a fashion that a cross section of the bump closer to a tip thereof is smaller.
    Type: Grant
    Filed: January 16, 2003
    Date of Patent: August 1, 2006
    Assignee: Advantest Corporation
    Inventor: Shigeru Matsumura
  • Patent number: 7084649
    Abstract: A method and apparatus are provided that make it possible to speedily measure, and obtain images of, the three-dimensional distribution of electric fields in integrated circuits, using electro-optic sampling. The sampling is performed using a plurality of electric field sensors, each comprising an electro-optic crystal layer, a light-reflecting layer that is in close contact with the electro-optic crystal layer, and a separation layer that is in close contact with the reflection layer, separating the reflection layer from the object to be measured.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: August 1, 2006
    Assignee: Communications Research Laboratory, Independent Administrative Institution
    Inventors: Tetsuya Kawanishi, Yoshiro Matsuo, Masayuki Izutsu