Abstract: Method and apparatus for sending packets using optimized PIO write sequences without sfences. Sequences of Programmed Input/Output (PIO) write instructions to write packet data to a PIO send memory are received at a processor supporting out of order execution. The PIO write instructions are received in an original order and executed out of order, with each PIO write instruction writing a store unit of data to a store buffer or a store block of data to the store buffer. Logic is provided for the store buffer to detect when store blocks are filled, resulting in the data in those store blocks being drained via PCIe posted writes that are written to send blocks in the PIO send memory at addresses defined by the PIO write instructions. Logic is employed for detecting the fill size of packets and when a packet's send blocks have been filled, enabling the packet data to be eligible for egress.

Abstract: A computer program product for processing input/output (I/O) data is provided for performing a method that includes receiving a transport control word (TCW) including an indirect data address including a starting location of a transport mode indirect data address list (TIDAL) of storage addresses, the TIDAL including a plurality of entries configured as transport mode indirect data address words (TIDAWs). The method includes accessing an entry of the TIDAL, which includes: 1) based on the entry of the TIDAL indicating that the address is a data address, gathering data from a data storage location corresponding to the data address, and accessing a next entry of the TIDAL, and 2) based on the entry of the TIDAL indicating that the address is an address of a next entry of the TIDAL, obtaining the next entry of the TIDAL from another storage location that is located non-contiguously to the entry storage location.

Abstract: System, methods and apparatus are described that offer improved performance of a camera control interface (CCIe) bus. A method of data communications includes transmitting a first synchronization code on a serial bus, establishing synchronization with a first device coupled to the serial bus in response to the first synchronization code, communicating with the first device over the serial bus in accordance with a first protocol, after establishing synchronization with the first device, transmitting a first unsynchronization code on the serial bus, where the unsynchronization code is configured to cause a loss of synchronization with the first device, transmitting a second synchronization code on the serial bus, establishing synchronization with a second device coupled to the serial bus in response to the second synchronization code, and communicating with the second device over the serial bus in accordance with a second protocol, after establishing synchronization with the second device.

Abstract: A system and method for making and using a computing system framework with unified storage, processing, and network switching fabrics are provided. Processing nodes, either physical or virtual, are associated with intra-module ports, inter-module ports, and local storage spaces. A plurality of processing nodes are linked through intra-module ports to form processing modules. A plurality of the processing modules are connected through inter-module ports to form the computing system. Network switch can be incorporated into intra-module or inter-module connections. Several inter-module connection schemes, which can be adapted to use with existing network packet routing algorithms, are disclosed. Each processing node needs only to keep track of the states of its directly connected neighbors, obviating the need for a high-speed connection to the rest processing nodes within the system. Dedicated network switching equipment can be flexibly employed and network capacity grows naturally as processing nodes are added.

Abstract: A machine has a bus, an input port connected to the bus to receive inbound network traffic, an output port connected to the bus to convey outbound network traffic and a processor complex connected to the bus. The processor complex is configured as a pipeline with individual processor cores assigned individual network traffic processing tasks. The pipeline includes a first set of processor cores to construct network traffic trees characterizing the inbound network traffic and the outbound network traffic. Each network traffic tree characterizes traffic type and traffic rate. A second set of processor cores enforces network traffic policies utilizing the network traffic trees. The network traffic policies apply traffic rate control by traffic type for the inbound network traffic and the outbound network traffic.

Abstract: A serial input/output (SIO) device with a serial peripheral interface (SPI) bus gateway controller. The gateway controller retrieves operation code (opcode) from a signal from the SPI bus and an address number from the signal; the gateway controller further compares the retrieved opcode with a restrict opcode, the retrieved address number with a restrict address number. When either the retrieved opcode matches the restrict opcode, or the retrieved address number matches the restrict address number, the gateway controller blocks the signal.

Abstract: Memory address generation for digital signal processing is described. In one example, a digital signal processing system-on-chip utilizes an on-chip memory space that is shared between functional blocks of the system. An on-chip DMA controller comprises an address generator that can generate sequences of read and write memory addresses for data items being transferred between the on-chip memory and a paged memory device, or internally within the system. The address generator is configurable and can generate non-linear sequences for the read and/or write addresses. This enables aspects of interleaving/deinterleaving operations to be performed as part of a data transfer between internal or paged memory. As a result, a dedicated memory for interleaving operations is not required. In further examples, the address generator can be configured to generate read and/or write addresses that take into account limitations of particular memory devices when performing interleaving, such as DRAM.

Abstract: In a method for ejecting a plurality of hot plug slots sharing a power controller, a processor receives a request to eject a plurality of hot plug slots, wherein the plurality of hot plug slots share a power controller and have at least two adapters present. A processor causes an OS to incrementally eject the at least two adapters, wherein ejecting an adapter comprises the OS stopping at least one driver of the adapter, and the OS generating a request to remove power from a hot plug slot. Responsive to a request by the OS to remove power from a hot plug slot, a processor generates a signal that prevents the OS from recognizing the adapter is present in the hot plug slot. Responsive to all device drivers for the at least two adapters being stopped, a processor causes power to be removed from the plurality of hot plug slots.

Abstract: A system includes a bus system, such as a LIN bus system. A number of components are connected to the bus system. A first component of the components is configured to detect a direction of a current to detect a location of the first component in the bus system. Each of the components can have a unique address.

Abstract: An embodiment includes a method includes designating a portion of a plurality of processing cores as an input/output (I/O) core and compiling a program source code to produce compiled program source code, including identifying an I/O operation region of the program source code, determining a number of I/O operations for the I/O operation region, and determining a number of system resources and system resource types for the I/O operation region. The method also includes executing the program source code using the plurality of processing cores, including scheduling the I/O operation region of the program source code on the I/O core of the plurality of processing cores.

Abstract: A RAID (redundant array of independent disks) hot spare (RHS) system and method that permits a daisy-chain of interconnected pass-thru disk drive controllers (PTDDCs) each connected to a SATA local disk drive (LDD) storage element (DSE) to support a hot spare disk (HSD) such that a failing disk drive (FDD) in the RAID array can be immediately replaced by a HSD within the PTDDC daisy-chain without operator intervention is disclosed. The PTDDCs within the daisy-chain are configured in RAID fashion to support mirroring of one or more drives in the PTDDC daisy-chain. The PTDDCs monitor functional status of LDDs attached to each PTDDC. FDD failure triggers activation of a HSD in the PTDDC daisy-chain and automatic mirror copying along the PTDDC daisy-chain of RAID data from a master disk drive (MDD) mirrored to the LDD. FDD-PTDDC and HSD-PTDDC LBA mapping registers are updated after mirror copying completes.

Abstract: A USB hub module which is configured to enable a vehicle's embedded USB host to connect to multiple mobile devices through a USB hub, regardless of whether the mobile devices are configured to act as USB hosts or USB devices, without providing USB OTG controllers or additional vehicle wiring or inhibiting functionality of consumer devices connected the module while one consumer device connected to the module operates in USB host mode. Preferably, the module is configured so that no additional cabling or hardware changes are required to the head unit. The module can be employed between the embedded USB host, USB hub and at least one consumer accessible USB port. When the consumer device is acting as a USB host, signals between the consumer device and the vehicle's embedded USB host are processed through a bridge, thereby rendering the consumer device compatible with the embedded USB host.

Abstract: A system is provided that includes a memory and one or more processors in communication with the memory. The one or more processors are configured to identify a set of targets and select a first value corresponding to a number of targets from the set of targets that can be concurrently disrupted. A second value is determined that is related to a number of disruptions actually occurring. A disruption request is received for a target of the set of targets. Thereafter, the first value is compared to the second value. Based on the comparison of the first and second values, it is determined whether to resist a requested disruption. If it is determined that the disruption is to be resisted, the requested disruption is resisted. If it is determined that the disruption is not to be resisted, at least one of the first value and the second value are adjusted.

Abstract: A method and system for transmission path optimization in an Internet Small Computer System Interface (iSCSI) storage area network architecture comprises a storage device downloading input/output (I/O) profiles from an SAN Software Defined Network (SDN) application and a host computer connected to the storage device via various transmission paths, to access a first virtual disk. The storage device analyzes iSCSI packets in the first virtual disk, and calculates I/O data of the first virtual disk and updated I/O data (for second I/O profile) at time intervals. The storage device can determine to change the first I/O profile of the first virtual disk as against the second I/O profile and the SAN SDN application can command an SDN controller to optimize the transmission path between the host computer and the first virtual disk by making the change, based on comparisons against the second I/O profile.

Abstract: For configuring wearable device, a method is disclosed that includes detecting a current wearable state for a wearable device, wherein the current wearable state is selected from the group consisting of on a person and off a person, and modifying a setting for the wearable device based on the detected wearable state.

Abstract: The disclosure relates to reconfigurable avionics equipment, subscribed to an onboard network such as an AFDX® network. The equipment has an architecture in two portions, a functional portion which makes it possible to perform the function proper to the piece of equipment and an interfacing portion, which allows the functional portion to communicate over the network. The interfacing portion includes a configuration file separate from the one used to configure the functional portion and able to be downloaded, using the network, independently of the latter.

Abstract: A system which is configured to enable a vehicle's embedded USB Host system to connect to multiple mobile devices through a USB Hub, regardless of whether the mobile devices are configured to act as USB Hosts or USB Devices, without the need to add or provide OTG controllers in the system or additional vehicle wiring, or inhibiting the functionality of any consumer devices operating in USB Device mode connected to a vehicle system Hub while another consumer device connected to the same Hub operates in USB Host mode. Preferably, the system is configured to provide that no additional cabling is required, and no hardware changes are required to be made to the HU. The system can be employed between a vehicle's embedded USB Host, USB Hub and at least one consumer accessible USB port.

Abstract: Certain embodiments herein relate to determining a type of input device from which user input is received. Input devices, such as keyboards, scanners, card readers, other keypad devices, etc., may send information to a computing device. The information may include one or more characters or signals, each of which may be received by the computing device after a delay. Such a delay may be analyzed to determine a source or type of user input device. A threshold time may be established such that an identification and number of characters received before the threshold time is reached may be used to determine the source or type of an input device. In example embodiments, a distinction between a bar code scanner and a keyboard, among other types of input devices used in a product shipping application, may be determined.

Abstract: A calibration system and method having a portable calibration apparatus comprising at least one input/output (I/O) channel to measure or simulate one or more functions of a remote device. The I/O channel being in coupled communication with a microcontroller. The portable calibration apparatus further comprising an internal power supply to provide power to the I/O channel. The internal power supply can also provide power to the microcontroller. The calibration system can also include a user interface to enable selection of at least one of a total number of functions of the I/O channel.

Abstract: The present disclosure includes a master device, a plurality of slave devices performing a communication through Profibus and a configuration tool providing network configuration information of Profibus DP by generating the network configuration information, wherein the configuration tool includes an automatic configuration module configured to request the master device of information relative to the plurality of slave devices in response to an automatic configuration command inputted through a user communication module, to receive the information and provide profiles of relevant types by determining the types of the plurality of slave devices using the received information, and a network configuration information configured to generate the network configuration information in response to the types and profiles determined by the automatic configuration module and to provide the network configuration information to the master device.