Abstract: Systems and methods of controlling operation of a connection device associated with a modular computing system are disclosed. For instance, data indicative of a connection between a first connection device and a second connection device can be obtained. The first connection device can be associated with a modular computing device, and the second connection device can be associated with a modular component to be implemented within the modular computing device. Each connection device can include a plurality of connector elements. Data indicative of one or more configuration parameters of the second connection device can be obtained. An operating configuration of the first connection device can be determined based at least in part on the data indicative of the one or more configuration parameters. Operation of the first connection device can be controlled based at least in part on the operating configuration.

Abstract: Operation of a multi-slice processor including execution slices and load/store slices, where the load/store slices are coupled to the execution slices via a results bus and the results bus includes segments assigned to carry results of a different instruction type, includes: receiving a producer instruction that includes an identifier of an instruction type and an identifier of the producer instruction, including storing the identifier of the instruction type and the identifier of the producer instruction in an entry of a register; receiving a source instruction dependent upon the result of the producer instruction including storing, in an issue queue, the source instruction, the identifier of the instruction type of the producer instruction, and an identifier of the producer instruction; and snooping the identifier of the producer instruction only from the segment of the results bus assigned to carry results of the instruction type of the producer instruction.

Abstract: A system and related method for I/O synchronization in a high integrity multi-core processing environment (MCPE) incorporates logical computing units (LCU) of two or more homogeneous processing cores, each core running a guest operating system (GOS) and user applications such that the homogeneous cores concurrently generate the same output data (which the GOS loads to an I/O synchronization engine (IOSE)) or receive the same output data from the IOSE. The IOSE verifies data integrity by comparing the concurrently received datasets and selects a verified dataset for routing to other cores or externally to the MCPE. The IOSE receives and atomically replicates input data for synchronous transfer to, and consumption by, the user applications running on the cores of the LCU.

Abstract: A peripheral device connected to a local electronic device which is connected to at least one communication network can communicate with a peripheral device attached to a remote electronic device as if the remote peripheral device was locally attached. Data designated for the remote peripheral device is received by a local virtual device object and transmitted to the remote electronic device via at least one of the electronic devices communication interfaces or peripheral devices. Data received by the remote electronic device's communication interface or peripheral device is written to the peripheral device at the remote electronic device by a virtual device object. For compensation of different transfer speeds or outages between the peripheral device and the communication interface or another peripheral device the virtual device provides the ability to utilize the virtual devices emulation driver that is attached to the virtual device object as an I/O buffer.

Abstract: Disclosed herein, in one example, is a device for aggregating networks in a vehicle and serving data, including video data, from those networks to a computer for integrating information from various systems in a vehicle, processing that information, and presenting the information to a user in a suitable format. The device for aggregating networks, in another example, is specific to a vehicle and serving data, including video data, from those networks to computers.

Abstract: A method for designing a system on a target device includes generating a timing netlist that reflects timing delays and timing relationships of a base configuration of a block in the system and a target configuration of the block in the system, wherein the base configuration of the block and the target configuration of the block implement different functionalities, and performing synthesis, placement, and routing on the system in response to the timing netlist.

Abstract: A chipset implemented in a server node of a server system and including an embedded management controller is disclosed. The chipset also includes a northbridge and southbridge. The embedded management controller collects inner-node information of the server node for server system management. The embedded management controller is coupled to a baseboard management controller, and the baseboard management controller is outside the server node and communicates with a remote console through network.

Abstract: One embodiment describes a reciprocal quantum logic (RQL) receiver system. The RQL system is configured to convert a serial input data stream provided from a serial data transmitter into an RQL data stream. The RQL receiver system includes a sampling controller configured to oversample the serial input data stream via a plurality of samples over each sampling window of an RQL clock signal to determine a transition sample corresponding to a transition in a digital value of the serial input data stream in a given one sampling window of the RQL clock signal. The RQL receiver system can be further configured to capture the digital value of the serial input data stream via a capture sample that is a predetermined number of samples subsequent to the transition sample in each sampling window of the RQL clock signal.

Abstract: A storage enclosure includes a plurality of hard drive sub-boards, each configured to include a plurality of hard drives. Each hard drive sub-board is coupled to one or more expanders, via and interface unit, with a set of dual-pass shielded cables. The expander includes a plurality of chipsets coupled to a complex logic device. Each chipset may communicate with a different subset of hard drives with potentially different timing characteristics. The dual-pass shielded cables may be arranged to mitigate these differences. In addition, pin assignments associated with the cables may be set in order to further mitigate the timing differences.

Abstract: The method relates to a Universal Plug and Play AV system, which comprises a media server included in a server device having a digital interface, to which a removable storage device is coupled, a media renderer included in a display device and a control point included in a control device for controlling the server device and the display device via Universal Plug and Play AV actions. The method comprises the steps of arranging an unmount icon in the display of the control device, unmounting the storage device in case said unmount icon is operated, and providing a feedback on the display device and/or the control device after said unmount action was performed on the server device.

Abstract: Method and apparatus for sending packets using optimized PIO write sequences without sfences. Sequences of Programmed Input/Output (PIO) write instructions to write packet data to a PIO send memory are received at a processor supporting out of order execution. The PIO write instructions are received in an original order and executed out of order, with each PIO write instruction writing a store unit of data to a store buffer or a store block of data to the store buffer. Logic is provided for the store buffer to detect when store blocks are filled, resulting in the data in those store blocks being drained via PCIe posted writes that are written to send blocks in the PIO send memory at addresses defined by the PIO write instructions. Logic is employed for detecting the fill size of packets and when a packet's send blocks have been filled, enabling the packet data to be eligible for egress.

Abstract: A computer includes: first and second connectors; and a data transmission path. The first connector includes: a first connector body to which at least a first module is capable of being attached; and a first electrode portion which is connected with the data transmission path. The first electrode portion is electrically connected with the first module when the first module is attached to the first connector body. The second connector includes: a second connector body to which at least the first module and a second module are alternatively capable of being attached; and a second electrode portion which is connected with the data transmission path. The second electrode portion is electrically connected with the second module when the second module is attached to the second connector body. The second electrode portion is electrically disconnected from the first module when the first module is attached to the second connector body.

Abstract: Apparatus and methods for USB hosts and USB devices to dynamically switch roles such that a product which initially operates as a USB host may instead operate as a USB device and vice versa. Products such as smartphones and tablets which initially operate as USB devices may dynamically switch roles to become USB hosts. Similarly, products such as PCs and in-vehicle infotainment systems which initially operate as USB hosts may dynamically switch roles to become USB devices. Dynamic USB role switching is permitted in a variety of topologies including those in which a direct connection exists between a host and a device as well as those in which a USB hub is present. In addition, such dynamic role switching may be performed in topologies which incorporate widely used USB Type A connectors and cables, thus avoiding the need for a special connector or cable.

Abstract: A computing device includes an inter-integrated circuit (I2C) module configured to perform I2C communication with an external device through a system management bus, a packet generator module configured to transmit a packet to the I2C module through the system management bus, and an I2C controller configured to control operations of the I2C module and the packet generator module. When the I2C module transmits a packet receiving signal to the I2C controller and the I2C controller does not receive the packet receiving signal for a set period of time, the I2C controller may reset the I2C module.

Abstract: Techniques for handling concurrent fatal events in a multicore execution environment are described. An example method for handling interrupts in a processor controlled device includes receiving an indication of a first fatal interrupt, determining if additional interrupts have occurred, serializing the handling of the first fatal interrupt and the additional interrupts, storing a serialized diagnostic information corresponding to each of the first fatal interrupt and the additional interrupts, and resetting the processor controlled device after storing the serialized diagnostic information corresponding to each of the first fatal interrupt and the additional interrupts.

Abstract: Latency reduction for direct memory access operations involving address translation is disclosed. Example methods disclosed herein to perform direct memory access (DMA) operations include initializing a ring of descriptors, the descriptors to index respective buffers for storing received data in a first memory. Such example methods also include causing prefetching of a first address translation associated with a second descriptor in the ring of descriptors to be performed after a first DMA operation is performed to store first received data in a first buffer indexed by a first descriptor in the ring of descriptors and before second received data to be stored in the first memory is received, the first address translation being associated with a second DMA operation for storing the second received data in the first memory.

Abstract: A peripheral interface chip and a data transmission method thereof are provided. The peripheral interface chip includes a switching circuit, a universal serial bus (USB) host controller, a keyboard controller and a microprocessor. The switching circuit receives a device identification transmitted from a USB device, and the device identification is used for determining whether the USB device is a keyboard device. When the USB device is the keyboard device, input data of the USB device is transmitted to a controller hub through a first USB interface, the switching circuit, the USB host controller, the microprocessor, the keyboard controller and a low pin count (LPC) interface.

Abstract: Systems and methods are provided that may be implemented to systems and methods that may be implemented to utilize direct memory access (DMA) remapping to control firmware updates and/or other configuration changes or device access control protocol for devices of an information handling system during the Unified Extensible Firmware Interface (UEFI) pre-boot phase before the booting the operating system (OS). The disclosed systems and methods may use DMA remapping during UEFI pre-boot to determine whether to allow or disallow pre-boot firmware updates and/or device configuration for hardware devices, and may be performed in the presence or absence of UEFI Secure Boot.

Abstract: In an example, a serial peripheral interface (SPI) flash memory controller includes a transmit first-in-first-out (FIFO) circuit and an SPI interface operable to provide an interface between the transmit FIFO and an SPI flash memory. The SPI flash memory controller further includes a random access memory (RAM) operable to store a memory interface file, an address interface of the RAM operable to receive a command from the transmit FIFO circuit, a data interface of the RAM operable to output a control word associated with the command. The SPI flash memory controller further includes state machine logic operable to set behavior of the SPI interface based on the control word output from the RAM, where the control word includes a data direction field, a data phase field, an addressing width field, an addressing phase field, and a command error field.

Abstract: In an embodiment of the invention, a method comprises: transmitting, by a host side, an exchange message protocol (EMP) command frame to a memory device side; informing, by the host side, the memory device side to process the command frame; executing, by the memory device side, the command frame; and transmitting, by the memory device side, an EMP response frame to the host side, in response to the command frame. In another embodiment of the invention, an apparatus comprises: a host side configured to transmit an exchange message protocol (EMP) command frame to a memory device side; wherein the host side is configured to inform the memory device side to process the command frame; wherein the memory device side is configured to execute the command frame; and wherein the memory device side is configured to transmit an EMP response frame to the host side, in response to the command frame.