Abstract: A method for execution by one or more processing modules of a distributed storage network includes encoding a data segment of data using a dispersed storage error coding function to produce a write threshold number of encoded data slices and identifying primary storage units available for storing the write threshold number of encoded data slices. The method further includes issuing a write slice request that includes a slice name and an encoded data slice corresponding to each of the available primary storage units. For those primary storage units that are unavailable the method continues by selecting a storage approach for storing an encoded data slice and selecting a foster storage unit. The method continues by issuing a write imposter slice request to each selected foster storage unit, where the imposter encoded data slice includes an information dispersal algorithm (IDA) index corresponding to the associated unavailable storage unit.

Abstract: A method and apparatus for continuous write and read operations during memory testing. The method comprises: controlling a signal generator; triggering a write address and a data field operation each memory cycle; triggering a write signal to write to a memory each memory clock cycle; and reading a read address and a read data operation to the memory. An additional embodiment provides an apparatus for advanced memory latency testing. The apparatus includes a data generator trigger in communication with a signal generator and an address generator trigger also in communication with the signal generator.

Abstract: Techniques for rebundling grid encoded data storage systems are described herein. A new grid of shards is created based in part on shards from a first grid of shards. The second grid of shards contains data shards, including one or more data shards from the first grid of shards, and derived shards that are indexed by row and column and is configured so that shards in the second grid are reproducible from shards in the same row using a first redundancy code and are also reproducible from shards in the same column using a second redundancy code. The derived shards of the second grid of shards are then derived from other shards in the second grid of shards using the first redundancy code and the second redundancy code.

Abstract: A codeword is generated from a message. One or more anchor values are appended to the codeword at predetermined anchor positions. Before the codeword is stored in a memory block, the locations and values of stuck cells in the memory block are determined. Based on the values and positions of the stuck cells, the values of the codeword are remapped so that values of the codeword that are the same as the values of the stuck cells are placed at the positions of the stuck cells. The remapped codeword is stored in the memory block. When the message is later read, the original codeword can be recovered from the remapped codeword based on the locations of the anchor values in the remapped codeword.

Abstract: Embodiments relate to a hardware circuit that is operable as a fixed point adder and a checksum adder. An aspect includes a driving of a multifunction compression tree disposed on a circuit path based on a control bit to execute one of first and second schemes of vector input addition and a driving of a multifunction adder disposed on the circuit path based on the control bit to perform the one of the first and second schemes of vector input addition.

Abstract: A communication system is configured to use coded modulation architecture using sparse regression codes. A transmitter includes a plurality of antenna and processing circuitry configured to: divide a data signal into a plurality of layers, allocate power individually to each of the plurality layers, encode a subset of the plurality of layers, the subset comprising a number of layers less than the whole, and interleave the subset of the plurality of layers. A receiver includes a plurality of antenna and processing circuitry configured to divide a received data signal into a plurality of layers and perform layer-by-layer decoding on the received data and control signals.

Abstract: A computer-based distributed error correction scheme with an efficient decoding algorithm is disclosed. The efficiency of the corresponding decoding algorithm, based on standard single source Reed-Solomon error correcting codes, makes the practical employment of the DECC feasible. Various implementation examples are also provided.

Abstract: A method, an apparatus, and a computer-readable medium for wireless communication are provided. In one aspect, the apparatus is configured to determine a number of data symbols for transmitting a data payload. The apparatus is configured to determine a number of payload bits for transmitting the data payload based on the determined number of data symbols. The apparatus is configured to transmit a data frame. The data frame includes a signal field and data symbols encoded based on the data payload, the determined number of data symbols, and the determined number of payload bits, in which the data symbols are encoded using LDPC encoding or BCC encoding.

Abstract: A method includes receiving, from a user device, a data object for storage. The method further includes determining dispersed storage error encoding parameters for the data object based on the virtual storage vault. The method further includes determining to adjust the pillar width number based on activation status of storage units in the set of storage units and others. When it is determined to adjust the pillar width number, adjusting the pillar width. The method further includes dispersed storage error encoding the data object in accordance with the decode threshold number, the encoding function, and the adjusted pillar width number. The method further includes sending a subset of encoded data slices from each of the sets of encoded data slices to active storage units of the set of storage units and sending an encoded data slice from each of the sets of encoded data slices to an active storage unit.

Abstract: A decoding apparatus includes a differential decoder, an error correction decoder and a controller. The differential decoder performs differential decoding according to a differential encoding dependency to generate a differential decoding result. The error correction decoder performs a decoding process on multiple packets that need to be corrected according to the differential decoding result to accordingly generate respective error correction records, wherein the packets are generated according to the differential decoding results, and the packets include a first packet and a second packet. When the error correction record of the first packet indicates that the decoding process of the first packet is unsuccessful, the controller generates a set of error position information according to the error correction record of the second packet, and requests the error correction decoder to perform another decoding process on the first packet according to the error position information.

Abstract: Data is received from a physical coding sublayer (PCS) of a physical layer, where the physical layer comprises a BASE-R physical layer. The data is used to generate a forward error correction (FEC) block comprising a shortened cyclic code comprising 32 rows of a particular number of bits, the particular number of bits comprise payload bits generated from output of the PCS and one or more bits of transcoding overhead, wherein the FEC block further comprises 32 parity bits at the end of the FEC block. The FEC block is scrambled using a pseudo-noise sequence. The FEC block is sent to a physical medium attachment (PMA) sublayer of the physical layer.

Abstract: The present invention relates to a device and method for transmitting/receiving a packet in a communication system. The present invention includes: the processes of determining at least one MPEG media transport (MMT) asset protected by an application layer forward error correction (AL-FEC); determining at least one FEC flow for transmitting the at least one MMT asset; determining the MMT asset transmitted from the at least one FEC flow in each case and determining an FEC coding structure to apply to the at least one FEC flow; producing at least one source flow by dividing the MMT asset transmitted from the at least one FEC flow on a transmission unit basis; and producing and transmitting at least one parity flow by performing AL-FEC encoding on the at least one source flow according to the FEC coding structure.

Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.

Abstract: Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane.

Abstract: Transmission control checking circuitry adds control check data to a transaction response which is received at a transaction master and compared with expected data at the transaction master. The expected data having control check data may be a unique transaction identifier. The transaction master generated the unique transaction identifier when it generated the transaction request and will check that the transaction responses include that unique transaction identifier. In this way, errors in the control of transmission of transactions (e.g., misrouting) may be detected.

Abstract: A transmission apparatus includes a first storage configured to store data received from external into a write enable area, a second storage configured to store the data in accordance with a write request and output a retry request in response to occurring an error of writing a first data included in the data, and a controller configured to read the data from the first storage and send the write request to the second storage, set an area of the first storage storing the first data to a write disable area in combination with stop sending the retry request to external when receiving the retry request from the second storage, and send the first data reading from the write disable area of the first storage to external in response to a read request from external.

Abstract: According to one aspect, bank-level fault management in a memory system is provided. The memory system includes a plurality of ranks, each rank including a plurality of memory devices each having a plurality of banks. A first error is detected in a first bank number of a first memory device of a rank. The first bank number of the first memory device is marked with a bank-level chip mark. The bank-level chip mark isolates declaration of an error condition to the first bank number. A bank-level fault management action is performed based on the bank-level chip mark to accommodate the error condition.

Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

Abstract: A built-in self-test circuit includes a command storage unit that stores commands inputted from an external device, an input/output control unit that controls the command storage unit to sequentially store the commands and sequentially output stored commands as internal commands in a test operation, and a command decoder unit that decodes the internal commands outputted from the command storage unit and outputs a test command.

Abstract: The complexity of sparse code multiple access (SCMA) decoding can be reduced by pruning codebooks to remove unlikely codewords prior to, or while, performing an iterative message passing algorithm (MPA). The pruned codebook is then used by to perform one or more iterations of MPA processing, thereby reducing the number codeword probabilities that are calculated for the corresponding SCMA layer. The pruned codebook also reduces the computational complexity of calculating codeword probabilities associated with other SCMA layers. The pruned codebook may be “reset” by reinserting the pruned codewords into the codebook after a final hard-decision for a given set of received samples is made, so that the pruning does not affect evaluation of the next set of samples.