Abstract: Embodiments are generally directed to errors and erasures decoding from multiple memory devices. An apparatus may include logic to store a portion of an error correction codeword in each of multiple memory devices, and logic to decode errors and erasures for the memory devices. The decoding of the errors and erasures includes reading the portions of the error correction codeword from a subset of the memory devices to generate a partial codeword, with the subset excluding at least one of the memory devices. The decoding of the errors and erasures further includes decoding errors and erasures of the plurality of memory devices based at least in part on the partial codeword if the errors and erasures can be decoded from the partial codeword, and, upon determining that the errors and erasures cannot be decoded from the partial codeword, then reading the one or more portions of the error correction codeword from the memory devices excluded from the first subset to generate a complete codeword.

Abstract: Methods and apparatuses for performing a quiesce operation during a processor recovery action is provided. A processor performs a processor recovery action. A processor retrieves a quiesce status of a computer system from a shared cache with a second processor. A processor determines a quiesce status of the first processor based, a least in part, on the retrieved quiesce status of the computer system.

Abstract: A scan chain latch circuit, a method of operating a latch circuit in a scan chain, and a computer-readable medium having stored thereon a data structure defining a scan chain latch circuit for instantiation on a semiconductor die are disclosed. In an embodiment, the scan chain latch circuit comprises a first latch for holding one data value, a second latch for holding another data value, and a multiplexor. The one data value is applied to a first data input of the multiplexor and the another data value is applied to a second data input of the multiplexor. An alternating clock signal is applied to a select input of the multiplexor to control the output of the multiplexor, wherein the output of the multiplexor toggles between the two data values held in the two latches at a defined frequency.

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a Low Density Parity Check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a plurality of modulation symbols, wherein the modulator is configured to map bits included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of each of the modulation symbols.

Abstract: Technologies are generally described for systems, devices, and methods effective to operate a memory device. A memory controller may compress initial data to produce compressed data. The memory controller may select a storage block in the memory device. The memory controller may identify one or more positions of defective cells in the selected storage block. The memory controller may manipulate the compressed data based on the identified one or more positions to produce manipulated data. The memory controller may store the manipulated data in the selected storage block.

Abstract: In one embodiment, a method for decoding data includes iteratively C1 decoding all first subsets of a set of data two or more times in each half iteration using two or more C1-decoding methods when a first subset is not decoded successfully using a first C1 decoding, determining whether to stop decoding the set of data after the C1 decoding and output results of the C1 decoding, incrementing a half iteration counter to indicate completion of a half iteration in response to decoding not being stopped, C2 decoding all second subsets of the set of data, determining whether to stop decoding the set of data after the C2 decoding and output results of the C2 decoding, incrementing the half iteration counter to indicate completion of another half iteration in response to decoding not being stopped, and outputting decoded data when all subsets of the set of data are decoded successfully.

Abstract: A computer-implemented method includes sending one or more network packets. Each of the one or more network packets includes a network packet header. The computer implemented method further includes receiving a negative acknowledgement list comprising the network packets not received. The computer-implemented method further includes, responsive to the receiving of a negative acknowledgment list: For each network packet of the negative acknowledgment list, transforming the network packet header into a modified packet header to yield a modified packet. The computer-implemented method further includes combining each modified packet into a modified packet list. The computer-implemented method further includes generating one or more repair packets. Each of the one or more repair packets further include a repair packet header and a portion of the modified packet list. The computer-implemented method further includes sending the one or more repair packets.

Abstract: A method, non-transitory computer readable medium, and storage management computing device that assists with distributing erasure coded fragments in geo-distributed storage nodes includes receiving an object and a storage reliability requirement from a client computing device. Erasure coding is performed on the received object using an erasure coding scheme. An erasure coding group from a plurality of erasure coding groups present in a plurality of geographically distributed storage nodes is determined based on the received storage reliability requirement and the erasure coding scheme. The erasure coded object is distributed to the determined erasure coding group from the plurality of erasure coding groups in the plurality of geographically distributed storage nodes.

Abstract: A method in a network node comprises generating a parity-check matrix for decoding a transmission scheme. The transmission scheme comprises a repetition code, an interleaver, and a modulation having a memory property. The parity-check matrix comprises a function of: a differentiator matrix, the differentiator matrix comprising an inverse of an accumulator matrix; a deinterleaver matrix, the deinterleaver matrix comprising an inverse of an interleaver matrix, the interleaver matrix comprising a square unitary permutation matrix for introducing randomness; and a repetition decoder matrix.

Abstract: Methods and apparatuses for performing a quiesce operation during a processor recovery action is provided. A processor performs a processor recovery action. A processor retrieves a quiesce status of a computer system from a shared cache with a second processor. A processor determines a quiesce status of the first processor based, a least in part, on the retrieved quiesce status of the computer system.

Abstract: A method is provided for processing broadcast data in a broadcast transmitter. Broadcast service data is randomized. The randomized broadcast service data is first-encoded to add parity data to the randomized broadcast service data. The first-encoded broadcast service data is second-encoded. The second-encoded broadcast service data is first interleaved. The first-interleaved broadcast service data is second-interleaved. Signaling data is encoded for signaling the broadcast service data. The encoded signaling data is third-interleaved. The third-interleaved signaling data is fourth interleaved. A frame is transmitted that is divided into a data region including the second-interleaved broadcast service data, a first signaling region including the fourth-interleaved signaling data and a second signaling region that includes at least one symbol that is used for synchronization and channel estimation. The frame includes known data.

Abstract: A communication control apparatus is provided for controlling recovery of data loss during data communication from a first communication device to a second communication device, which includes an obtaining section configured to obtain a temporal change in a communication load between the first communication device and the second communication device. The communication control apparatus also includes a change section configured to dynamically change a permitted time and an interval between transmissions on the basis of the temporal change in the communication load, the permitted time being a time that is permitted to be used by the second communication device for recovery of data loss and the interval between transmissions being an interval between transmissions of a retransmission request message. The communication control apparatus further includes a retransmission control section configured to control transmission of the retransmission request message in accordance with the interval between transmissions.

Abstract: The invention relates to a method for encoding MSR (Minimum-storage Regenerating) codes, which comprises the following steps of: acquiring n first data packets which are represented by Si, i=1, 2, . . . , n; setting n storage nodes and a positive integer k, wherein n=2K; respectively adding a specified number of 0 bits on data heads or data tails of subsequent successive k first data packets by taking the next first data packet of the ith first data packet as a starting point, acquiring k second data packets, and acquiring an encoded data packet by computing the k second data packets; repeating the above steps and acquiring n encoded data packets which are represented by Pi, i=1, 2, . . . , n; and storing the ith first data packet and the encoded data packet acquired by taking the next first data packet of the first data packet as the starting point into the ith storage node.

Abstract: A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Abstract: Method of identification and compensation for inversion of the input bit stream when decoding LDPC codes includes obtaining a code word of the LDPC code from a demodulator output and writing the code word into a buffer memory, decoding the code word, calculating a syndrome for each iteration when decoding, making an analysis of converging the weight of the syndrome, generating an inversion feature for the input bit stream based on this analysis, continuing the decoding, if the inversion feature for the input bit stream does not give evidence of detecting inversion, resetting, if the inversion feature for the input bit stream shows inversion, the LDPC decoder and analysis parameters for the convergence of the weight of the syndrome, reading next code word from the buffer memory, and producing an inversion of this code word, and feeding the word to the decoder input to implement the next decoding operation.

Abstract: Systems and methods for internal copy-back with read-verify are described. In one embodiment, a storage device includes a controller to select a first single level cell (SLC) page of a plurality of SLC pages on the storage device to transfer to a triple level cell (TLC) page. The controller, in conjunction with an error correcting code (ECC) decoder, read-verifies the first SLC page. Read-verifying the first SLC page includes reading the first SLC page to an internal page buffer, decoding the first SLC page read into the internal page buffer, determining a number of errors contained in the first SLC page based at least in part on the decoding, and verifying whether the number of errors contained in the first SLC page satisfies an error threshold. The controller transfers the first SLC page to the TLC page according to a result of read-verifying the first SLC page.

Abstract: A block of data is partitioned into a plurality of sub-blocks each including a logical array having rows and columns of data symbols, encoded using a row linear block code and a column linear block code. Each product codeword includes a logical array of code symbols having rows which include respective row codewords and columns which include respective column codewords. The product codewords are encoded by encoding groups of L symbols, using a rate-L/(L+M) linear block code to produce a plurality of (L+M)-symbol codewords which are logically arranged in nQ encoded blocks (where n is an integer greater than zero). Each of the nQ encoded blocks includes an array having rows and columns of code symbols in which each column includes a codeword of the column code.

Abstract: Aspects of the disclosure involve memory data scrubber circuits configured to perform memory data scrubbing operations in a processor-based memory to provide data error correction in response to periodic memory controller wake-up periods. Memory data scrubbing is performed to correct errors in data words stored in memory. Memory data scrubbing is initiated in the memory to conserve power in response to periodic memory controller wake-up periods during processor idle periods. Further, in certain aspects disclosed herein, the memory data scrubber circuit is provided as a separate system outside of the memory controller in the memory system. In this manner, power consumption can be further reduced, because the memory data scrubber circuit can continue with memory data scrubbing operations in the memory independent of the memory controller operation, and after the memory controller access commands issued during the wake-up period are completed and the memory controller is powered-down.

Abstract: A block of data is partitioned into a plurality of sub-blocks each including a logical array having rows and columns of data symbols, encoded using a row linear block code and a column linear block code. Each product codeword includes a logical array of code symbols having rows which include respective row codewords and columns which include respective column codewords. The product codewords are encoded by encoding groups of L symbols, using a rate-L/(L+M) linear block code to produce a plurality of (L+M)-symbol codewords which are logically arranged in nQ encoded blocks (where n is an integer greater than zero). Each of the nQ encoded blocks includes an array having rows and columns of code symbols in which each column includes a codeword of the column code.